Subjects : Parallel mode
| Type | Year | Title | Cited | Download |
|---|---|---|---|---|
| Conference | 2006 | 32Bit SIMSD Path Architecture For High Energy Efficiency Using Single/Parallel Mode Bit and 2 Step Gating Technique Yang Yil Suk 한국반도체 학술 대회 (KCS) 2006, pp.1-2 | ||
| Journal | 2005 | Experimental Evaluation of Arrayed Microcolumns with Monolithic Structure Jeong Jin Woo Japanese Journal of Applied Physics, v.44, no.7B, pp.5565-5569 | 3 | 원문 |
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| Type | Year | Research Project | Primary Investigator | Download |
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