Subjects : Reduced Instruction set computer (RISC)
| Type | Year | Title | Cited | Download |
|---|---|---|---|---|
| Journal | 2012 | Multicore Flow Processor with Wire-Speed Flow Admission Control Doo Kyeong Hwan ETRI Journal, v.34, no.6, pp.827-837 | 5 | 원문 |
| Conference | 2012 | Analysis of an Asynchronous RISC Processor Based on EISC Instruction Set Architecture Oh Myeong-Hoon International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) 2012, pp.1-3 | ||
| Journal | 2011 | A Multi-Band OFDM Ultra-Wideband SoC in 90 nm CMOS Technology 김도훈 IEEE Transactions on Consumer Electronics, v.57, no.3, pp.1064-1070 | 6 | 원문 |
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| Type | Year | Research Project | Primary Investigator | Download |
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