Subjects : period jitter
| Type | Year | Title | Cited | Download |
|---|---|---|---|---|
| Conference | 2014 | A 230ns settling time type-I PLL with 0.96mW TDC power and simple T<inf>V</inf> calculation algorithm Lee Ja Yol International Midwest Symposium on Circuits and Systems (MWSCAS) 2014, pp.370-373 | 1 | 원문 |
| Status | Year | Patent Name | Country | Family Pat. | KIPRIS |
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| Type | Year | Research Project | Primary Investigator | Download |
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