Subjects : Frequency offset tolerance
| Type | Year | Title | Cited | Download |
|---|---|---|---|---|
| Conference | 2006 | A 1 .25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution 성창경 International Symposium on Circuits and Systems (ISCAS) 2006, pp.2113-2116 | 3 |
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| Type | Year | Research Project | Primary Investigator | Download |
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