상세정보
등록 전계효과 트랜지스터의 제조방법
- 출원번호
- 11180726 (2005.07.14)
- 공개번호
- 20060121658 (2006.06.08)
- 등록번호
- 7183149 (2007.02.27)
- 출원국
- 미국
- 협약과제
- 04MB1200, 60GHz Pico Cell 통신용 SoP(구:60GHz 광대역 무선 LAN 기술 개발), 조경익
- 초록
- Provided is a method of manufacturing a field effect transistor (FET). The method includes steps of: forming an ohmic metal layer on a substrate in source and drain regions; sequentially forming an insulating layer and a multilayered resist layer on the entire surface of the resultant structure and simultaneously forming resist patterns having respectively different shapes in both a first region excluding the ohmic metal layer and a second region excluding the ohmic metal layer, wherein a lowermost resist pattern is exposed in the first region, and the insulating layer is exposed in the second region; exposing the substrate and the insulating layer by simultaneously etching the exposed insulating layer and the exposed lowermost resist pattern using the resist patterns as etch masks, respectively; performing a recess process on the exposed substrate and etching the exposed insulating layer to expose the substrate; and forming gate recess regions having different etching depths from each other over the substrate, depositing a predetermined gate metal, and removing the resist patterns. In this method, transistors having different threshold voltages can be manufactured without additional mask patterns using the least number of processes, with the results that the cost of production can be reduced and the stability and productivity of semiconductor devices can be improved.
- 패밀리
| 구분 | 특허 | 출원국 | KIPRIS |
|---|---|---|---|
| 등록 | 전계효과 트랜지스터의 제조방법 | 대한민국 | KIPRIS |
| 등록 | 전계효과 트랜지스터의 제조방법 | 일본 |