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Registered Triple well SCR for ESD protection

정전기 방전을 방지하기 위한 3중 웰 SCR
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Inventors
Kim Kwi Dong, Kwon Jong-Kee, Kim Jongdae
Application No.
12018317 (2008.01.23)
Publication No.
20080128817 (2008.06.05)
Registration No.
7576961 (2009.08.18)
Country
UNITED STATES
Project Code
03MB5300, Development of semiconductor circuit design based on the nano-scaled device, Kim Jongdae
Abstract
Provided is an electrostatic discharge (ESD) protection circuit using a silicon controlled rectifier (SCR), which is applied to a semiconductor integrated circuit (IC). A semiconductor substrate has a triple well structure such that a bias is applied to a p-well corresponding to a substrate of a ggNMOS device. Thus, a trigger voltage of the SCR is reduced. In addition, two discharge paths are formed using two SCRs including PNP and NPN bipolar transistors. As a result, the ESD protection circuit can have greater discharge capacity.