상세정보
등록 정전기 방전을 방지하기 위한 3중 웰 SCR
- 출원번호
- 12018317 (2008.01.23)
- 공개번호
- 20080128817 (2008.06.05)
- 등록번호
- 7576961 (2009.08.18)
- 출원국
- 미국
- 협약과제
- 03MB5300, 나노소자기반 회로 설계기술 개발, 김종대
- 초록
- Provided is an electrostatic discharge (ESD) protection circuit using a silicon controlled rectifier (SCR), which is applied to a semiconductor integrated circuit (IC). A semiconductor substrate has a triple well structure such that a bias is applied to a p-well corresponding to a substrate of a ggNMOS device. Thus, a trigger voltage of the SCR is reduced. In addition, two discharge paths are formed using two SCRs including PNP and NPN bipolar transistors. As a result, the ESD protection circuit can have greater discharge capacity.
- KSP 제안 키워드
- Bipolar transistors, Controlled Rectifier, ESD protection, ESD protection circuit, Electro-Static Discharge(ESD), Electrostatic discharge (ESD) protection, Electrostatic discharge (ESD) protection circuit, Integrated circuit, Protection circuit, Semiconductor integrated, Silicon Controlled Rectifier(SCR), Well structure, discharge capacity, p-well, semiconductor substrate, trigger voltage