상세정보
등록 고에너지 효율 내장형 프로세스 구조
- 출원번호
- 11520177 (2006.09.13)
- 공개번호
- 20070150763 (2007.06.28)
- 등록번호
- 7805620 (2010.09.28)
- 출원국
- 미국
- 협약과제
- 05MB1100, 나노소자기반 회로 설계기술 개발, 김종대
- 초록
- Provided is a highly energy-efficient processor architecture. The architecture employs 2-stage dynamic voltage scaling (DVS) and a sleep mode for high energy efficiency, dynamically controls the power supply voltage and activation of an embedded processor with instructions, and thus can prevent performance deterioration while reducing power consumption.A highly energy-efficient processor employing the processor architecture includes: a function unit block for performing an operation according to instructions input from the outside; at least one peripheral unit block for performing data communication with an external device; an instruction decoder for interpreting the input instructions and determining operation modes of the function unit block and peripheral unit block required for executing the interpreted instructions; a function unit block driver for applying a different power supply voltage according to the operation mode of the function unit block to the function unit block; and a peripheral unit block driver for applying a different power supply voltage according to the operation mode of the peripheral unit block to the peripheral unit block.
- KSP 제안 키워드
- Dynamic voltage scaling, Embedded processor, Energy Efficiency, Instruction Decoder, Power Consumption, Processor architecture, Reducing power, Sleep mode, Supply voltage, Voltage scaling, data communication, dynamic voltage, energy-efficient, function unit, high energy, high energy efficiency, operation mode, performance deterioration, power supply