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Detail
Registered MULTI-BIT PIPELINE ANALOG-TO-DIGITAL CONVERTER HAVING SHARED AMPLIFIER STRUCTURE
- Inventors
- Young-Deuk Jeon, Seung-Chul Lee, Kim Kwi Dong, Kwon Jong-Kee, Kim Jongdae
- Application No.
- 11695143 (2007.04.02)
- Publication No.
- 20080068237 (2008.03.20)
- Registration No.
- 7397409 (2008.07.08)
- Country
- UNITED STATES
- Project Code
- 06MB1100, Development of semiconductor circuit design based on the nano-scaled device, Kim Jongdae
- Abstract
- A multi-bit pipeline analog-to-digital converter (ADC) having a shared amplifier structure includes: a sample-and-hold amplifier (SHA) for sampling and holding an input analog voltage and removing a sampling error of the input voltage; N-bit flash ADCs of first to K-th stages receiving analog signals, converting them into digital signals and outputting the digital signals; N-bit multiplying digital-to-analog converters (MDACs) of first to K-th stages converting differences between the digital signals output from the N-bit flash ADCs and output signals of preceding stages back into analog signals and outputting the analog signals; and a three-stage amplifier connected to an output of the N-bit MDAC of the first stage at a first clock and an output of the SHA at a second clock, wherein intergers N>= and K>=2. An amplifier can be shared between an SHA and an MDAC of a first stage, thereby reducing power consumption and chip size.In the multi-bit pipeline ADC, an amplifier can be shared between an SHA consuming much power and an MDAC of a first stage, so that power consumption and chip size can be reduced.
- KSP Keywords
- Analog signal, Analog-to-digital converters(ADCs), Digital Signal, First stage, Input voltage, Multiplying Digital-To, Pipeline ADC, Power Consumption, Reducing power, Sample-and-Hold, Sample-and-hold amplifier, Sampling error, Shared amplifier, Three-stage, analog-to-digital, digital converter, digital-to-analog(DAC), digital-to-analog converters, three-stage amplifier