상세정보
등록 멀티-비트 파이프라인 아날로그-디지털 변환기에서의 다단 증폭기 공유 기법
- 출원번호
- 11695143 (2007.04.02)
- 공개번호
- 20080068237 (2008.03.20)
- 등록번호
- 7397409 (2008.07.08)
- 출원국
- 미국
- 협약과제
- 06MB1100, 나노소자기반 회로 설계기술 개발, 김종대
- 초록
- A multi-bit pipeline analog-to-digital converter (ADC) having a shared amplifier structure includes: a sample-and-hold amplifier (SHA) for sampling and holding an input analog voltage and removing a sampling error of the input voltage; N-bit flash ADCs of first to K-th stages receiving analog signals, converting them into digital signals and outputting the digital signals; N-bit multiplying digital-to-analog converters (MDACs) of first to K-th stages converting differences between the digital signals output from the N-bit flash ADCs and output signals of preceding stages back into analog signals and outputting the analog signals; and a three-stage amplifier connected to an output of the N-bit MDAC of the first stage at a first clock and an output of the SHA at a second clock, wherein intergers N>= and K>=2. An amplifier can be shared between an SHA and an MDAC of a first stage, thereby reducing power consumption and chip size.In the multi-bit pipeline ADC, an amplifier can be shared between an SHA consuming much power and an MDAC of a first stage, so that power consumption and chip size can be reduced.
- KSP 제안 키워드
- Analog signal, Analog to digital converter(ADC), Digital Signal, Digital to Analog Converter, First stage, Input voltage, Multiplying Digital-To, Pipeline ADC, Power Consumption, Reducing power, Sample-and-hold amplifier, Sampling error, Shared amplifier, Three-stage, analog-to-digital, digital converter, digital-to-analog(DAC), sample-and-hold, three-stage amplifier