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Registered METHOD OF CONTROLLING PIPELINE ANALOG-TO-DIGITAL CONVERTER AND PIPELINE ANALOG-TO-DIGITAL CONVERTER IMPLEMENTING THE SAME
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METHOD OF CONTROLLING PIPELINE ANALOG-TO-DIGITAL CONVERTER AND PIPELINE ANALOG-TO-DIGITAL CONVERTER IMPLEMENTING THE SAME
- Inventors
- Young-Deuk Jeon, Cho Young Kyun, Seung-Chul Lee, Kim Kwi Dong, Kwon Jong-Kee, Kim Jongdae
- Application No.
- 12027495 (2008.02.07)
- Publication No.
- 20090033530 (2009.02.05)
- Registration No.
- 7583219 (2009.09.01)
- Country
- UNITED STATES
- Project Code
- 07MB2600, Components/Module technology for Ubiquitous Terminals, Kim Jongdae
- Abstract
- Provided are a pipeline Analog-to-Digital Converter (ADC) without a front-end Sample-and-Hold Amplifier (SHA) and a method of controlling the same. The method includes the steps of: simultaneously sampling, at an ADC and a residual signal generator included in a first stage, an analog input signal and respectively generating a first sampling value and a second sampling value; holding, at the residual signal generator, the second sampling value, and simultaneously amplifying and converting, at the ADC, the first sampling value into a corresponding digital code; and generating, at the residual signal generator, a residual signal using the digital code. The pipeline ADC and method of controlling the same minimize sampling mismatch caused by removing a front-end SHA, thereby ensuring stable performance without a front-end SHA. Since a front-end SHA is not used, it is possible to reduce chip size and power consumption, and improve the performance of the ADC.
- KSP Keywords
- Analog input, Analog-to-digital converters(ADCs), Digital code, First stage, Front-End, Pipeline ADC, Power Consumption, Residual signal, Sample-and-Hold, Sample-and-hold amplifier, Sampling value(SV), Signal Generator, analog-to-digital, digital converter, input signal, stable performance