상세정보
등록 파이프라인 아날로그-디지털 변환기 제어 방법 및 이를 구현한 파이프라인 아날로그-디지털 변환기
- 출원번호
- 12027495 (2008.02.07)
- 공개번호
- 20090033530 (2009.02.05)
- 등록번호
- 7583219 (2009.09.01)
- 출원국
- 미국
- 협약과제
- 07MB2600, 유비쿼터스 단말용 부품 모듈, 김종대
- 초록
- Provided are a pipeline Analog-to-Digital Converter (ADC) without a front-end Sample-and-Hold Amplifier (SHA) and a method of controlling the same. The method includes the steps of: simultaneously sampling, at an ADC and a residual signal generator included in a first stage, an analog input signal and respectively generating a first sampling value and a second sampling value; holding, at the residual signal generator, the second sampling value, and simultaneously amplifying and converting, at the ADC, the first sampling value into a corresponding digital code; and generating, at the residual signal generator, a residual signal using the digital code. The pipeline ADC and method of controlling the same minimize sampling mismatch caused by removing a front-end SHA, thereby ensuring stable performance without a front-end SHA. Since a front-end SHA is not used, it is possible to reduce chip size and power consumption, and improve the performance of the ADC.
- KSP 제안 키워드
- Analog input, Analog to digital converter(ADC), Digital code, First stage, Front-End, Input signal, Pipeline ADC, Power Consumption, Residual signal, Sample-and-hold amplifier, Sampling value(SV), Signal Generator, analog-to-digital, digital converter, sample-and-hold, stable performance