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Detail
Registered PROGRAMMABLE LOGIC BLOCK OF FPGA USING PHASE-CHANGE MEMORY DEVICE
- Inventors
- Byoung Gon Yu, Yoon Sung Min, 김용주, Park Young Sam, Lee Seung-Yun, Soon-Won Jung
- Application No.
- 12633731 (2009.12.08)
- Publication No.
- 20100148821 (2010.06.17)
- Registration No.
- 7911227 (2011.03.22)
- Country
- UNITED STATES
- Abstract
- Provided is a programmable logic block of a field-programmable gate array (FPGA). The programmable logic block includes a pull-up access transistor connected to a power source, an up-phase-change memory device connected to the pull-up access transistor, a down-phase-change memory device connected to the up-phase-change memory device, an output terminal between the up-phase-change memory device and the down-phase-change memory device, and a pull-down access transistor connected to the down-phase-change memory device and a ground. The resistance values of the up-phase-change memory device and the down-phase-change memory device are individually programmed.
- KSP Keywords
- Access transistor, Field-Programmable Gate Array(FPGA), Gate array, Phase Change Material(PCM), Phase change, Programmable Logic, Pull-down, Pull-up, field-programmable, memory device, power source, programmable gate