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Registered DIGITAL PHASE-LOCKED LOOP

디지털 위상 고정 루프
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Inventors
Boo Hyun Ho, Min Byung Hun, Kim Cheon Soo, Yu Hyun Kyu, Duong Quoc Hoang
Application No.
14028707 (2013.09.17)
Publication No.
20140266354 (2014.09.18)
Registration No.
9013216 (2015.04.21)
Country
UNITED STATES
Project Code
11MB5600, RFIC/PAM Development for 2G/3G/4G Mobile Communication Device, Yu Hyun Kyu
Abstract
Disclosed is a digital phase-locked-loop including: a time-to-digital converter (TDC) configured to output a digital bit based on an input clock and a reference clock, in which the TDC includes: a first arbiter group configured to compensate for a phase difference between the input clock and the reference clock with a first average offset and output a first logic value; a second arbiter group configured to compensate for a phase difference between the input clock and the reference clock with a second average offset and output a second logic value; and a signal processor configured to output the digital bit based on the first and second logic values.
KSP Keywords
Phase Difference, Phase locked loop(PLL), Reference clock, Signal processor, Time-to-Digital Converter, Time-to-digital, digital converter, digital phase locked loop(DPLL)