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구분 출원국
출원년도 ~ 키워드

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등록 캐시 일치성을 갖는 캐시 제어 장치

캐시 일치성을 갖는 캐시 제어 장치
이미지 확대
발명자
한진호, 신경선, 권영수, 변경진, 엄낙웅
출원번호
14253349 (2014.04.15)
공개번호
20150143049 (2015.05.21)
등록번호
9824017 (2017.11.21)
출원국
미국
협약과제
13VC2300, 에너지 스케일러블 벡터 프로세서 선행기술, 엄낙웅
초록
Provided is a cache control apparatus and method that, when a plurality of processors read a program from the same memory in a chip, maintain coherency of data and an instruction generated by a cache memory. The cache control apparatus includes a coherency controller client configured to include an MESI register, which is included in an instruction cache, and stores at least one of a modified state, an exclusive state, a shared state, and an invalid state for each line of the instruction cache, and a coherency interface connected to the coherency controller and configured to transmit and receive broadcast address information, read or write information, and hit or miss information of another cache to and from the instruction cache.