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Detail
Registered CACHE CONTROL APPARATUS AND METHOD
- Inventors
- Han Jin Ho, Shin Kyoung Seon, Kwon Young-Su, Nak Woong Eum, Byun Kyung Jin
- Application No.
- 14253349 (2014.04.15)
- Publication No.
- 20150143049 (2015.05.21)
- Registration No.
- 9824017 (2017.11.21)
- Country
- UNITED STATES
- Project Code
- 13VC2300, Energy Scalable Vector Processor - Primary Technology, Nak Woong Eum
- Abstract
- Provided is a cache control apparatus and method that, when a plurality of processors read a program from the same memory in a chip, maintain coherency of data and an instruction generated by a cache memory. The cache control apparatus includes a coherency controller client configured to include an MESI register, which is included in an instruction cache, and stores at least one of a modified state, an exclusive state, a shared state, and an invalid state for each line of the instruction cache, and a coherency interface connected to the coherency controller and configured to transmit and receive broadcast address information, read or write information, and hit or miss information of another cache to and from the instruction cache.
- KSP Keywords
- Cache Memory, Shared state, instruction cache