BROWSE
Detail
Registered APPARATUS FOR ERROR SIMULATION AND METHOD THEREOF
- Inventors
- Han Jin Ho, Byun Kyung Jin, Kwon Young-Su
- Application No.
- 14677297 (2015.04.02)
- Publication No.
- 20150293827 (2015.10.15)
- Registration No.
- 9632894 (2017.04.25)
- Country
- UNITED STATES
- Project Code
- 13VC4400, Robust Fault-Resilient SW For Vehicle Processors, Kwon Young-Su
- Abstract
- The present invention relates to an apparatus for computing an error rate comprising: a first circuit interface being connected to a first sub-circuit receiving data and computing output data through a predetermined computation process; a second circuit interface and being connected to a first test circuit receiving the same data, which is inputted to the first sub-circuit, and computing output data through the predetermined computation process; an error injecting part injecting an error to the first test circuit; an error detecting part comparing output data of the first sub-circuit to output data of the first test circuit; and an error rate computing part computing input node error probability of the first sub-circuit by statistic processing of the compared result. The apparatus and method for computing error rate of the present invention is able to shorten the time required to obtain error probability, compared to the direct simulation of the full circuit.
- Family
| Status | Patent | Country | KIPRIS |
|---|---|---|---|
| Registered | 에러 시뮬레이션 장치 및 그 방법 | KOREA | KIPRIS |