BROWSE
Detail
Registered METHOD AND APPARATUS FOR INJECTING FAULT AND ANALYZING FAULT TOLERANCE
- Inventors
- Yong Cheol Peter Cho, Kwon Young-Su, Nak Woong Eum, Byun Kyung Jin
- Application No.
- 15154829 (2016.05.13)
- Publication No.
- 20160334467 (2016.11.17)
- Registration No.
- 10489520 (2019.11.26)
- Country
- UNITED STATES
- Project Code
- 14PS5300, Robust Fault-Resilient SW For Vehicle Processors, Kwon Young-Su
- Abstract
- Disclosed herein is a method and apparatus for injecting a fault and analyzing fault tolerance. The fault tolerance analysis apparatus extracts design information from a design. The fault tolerance analysis apparatus may inject a fault into a simulation of the design based on the extracted design information and parameters, and analyzes an influence of the fault on the simulation. Accordingly, in accordance with the fault tolerance analysis apparatus, fault tolerance for the fault injected into the simulation is analyzed, and the effect of the fault tolerance mechanism provided in the design is analyzed.
- KSP Keywords
- Design information, Design method, Fault Injection, Fault tolerance, Fault tolerance analysis, Fault tolerance mechanism, Tolerance mechanism, processor design, tolerance analysis
- Family
| Status | Patent | Country | KIPRIS |
|---|---|---|---|
| Registered | METHOD AND APPARATUS FOR FAULT INJECTION AND FAULT TOLERANCE ANALYSIS | KOREA | KIPRIS |