상세정보
등록 Method and apparatus for Fault Injection and Fault Tolerance Analysis of a VLSI processor design
이미지 확대
Method and apparatus for Fault Injection and Fault Tolerance Analysis of a VLSI processor design
- 출원번호
- 15154829 (2016.05.13)
- 공개번호
- 20160334467 (2016.11.17)
- 등록번호
- 10489520 (2019.11.26)
- 출원국
- 미국
- 협약과제
- 14PS5300, 자동차 전장시스템의 실시간 오류 감지 및 복구 프로세서 SW 개발, 권영수
- 초록
- Disclosed herein is a method and apparatus for injecting a fault and analyzing fault tolerance. The fault tolerance analysis apparatus extracts design information from a design. The fault tolerance analysis apparatus may inject a fault into a simulation of the design based on the extracted design information and parameters, and analyzes an influence of the fault on the simulation. Accordingly, in accordance with the fault tolerance analysis apparatus, fault tolerance for the fault injected into the simulation is analyzed, and the effect of the fault tolerance mechanism provided in the design is analyzed.
- KSP 제안 키워드
- Design information, Design method, Fault Injection, Fault tolerance, Fault tolerance analysis, Fault tolerance mechanism, Tolerance mechanism, processor design, tolerance analysis
- 패밀리
| 구분 | 특허 | 출원국 | KIPRIS |
|---|---|---|---|
| 등록 | 결함 주입 및 결함 감내 분석을 위한 방법 및 장치 | 대한민국 | KIPRIS |