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Detail
Registered PHASE LOCKED LOOP FOR REDUCING FRACTIONAL SPUR NOISE
- Inventors
- 이민재, Kim Cheon Soo, Lee Ja Yol, 고준수, 강재현
- Application No.
- 15185438 (2016.06.17)
- Publication No.
- 20160373115 (2016.12.22)
- Registration No.
- 9735788 (2017.08.15)
- Country
- UNITED STATES
- Project Code
- 14MS1900, High Speed Long Range Wi-Fi Development for Future M2M Service, Kim Cheon Soo
- Abstract
- Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal, the PLL including a first phase interpolator configured to generate a first interpolator clock signal that has a first time delay from the output clock signal and a second phase interpolator configured to generate a second interpolator clock signal that has a second time delay from the output clock signal. The PLL controls a frequency of the output clock signal based on a multiplexing the first interpolator clock signal and the second interpolator clock signal.
- KSP Keywords
- Fractional spur, Reference clock, Second phase, Time Delay, clock signal, phase interpolator, phase locked, phase-locked loop(PLL), signal based, spur noise
- Family
| Status | Patent | Country | KIPRIS |
|---|---|---|---|
| Registered | 프랙셔널 스퍼 잡음을 감소시키기 위한 위상 고정 루프 | KOREA | KIPRIS |