위상변위를 사용한 디지털 주파수합성기에서 프랙셔널스퍼 감쇄기술
이민재, 이자열, 김천수, 고준수, 강재현
- 9735788 (2017.08.15)
14MS1900, 미래 사물지능통신 서비스를 위한 초고속 광역 와이파이 기술개발,
- Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal, the PLL including a first phase interpolator configured to generate a first interpolator clock signal that has a first time delay from the output clock signal and a second phase interpolator configured to generate a second interpolator clock signal that has a second time delay from the output clock signal. The PLL controls a frequency of the output clock signal based on a multiplexing the first interpolator clock signal and the second interpolator clock signal.
- KSP 제안 키워드
- Fractional spur, Phase locked loop(PLL), Reference clock, Second phase, Time Delay, clock signal, phase interpolator, phase locked, signal based, spur noise