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Detail
Registered PROCESSOR SYSTEM AND FAULT DETECTION METHOD THEREOF
- Inventors
- Kwon Young-Su, Nak Woong Eum, Byun Kyung Jin
- Application No.
- 15432588 (2017.02.14)
- Publication No.
- 20170262011 (2017.09.14)
- Registration No.
- 10430301 (2019.10.01)
- Country
- UNITED STATES
- Project Code
- 15PS5300, Robust Fault-Resilient SW for Vehicle Processors, Kwon Young-Su
- Abstract
- Provided is a processor system including a first processor driven by a first driving voltage and a first driving clock, a second processor driven by a second driving voltage and a second driving clock and configured to perform an identical task to the first processor, and a defect detector configured to perform level synchronization or clock domain synchronization on a first output signal provided from the first processor and a second output signal provided from the second processor to compare the first and second output signals, wherein the first and second driving voltages are respectively provided from mutually independent power supply sources and the first and second driving clocks are respectively provided from mutually independent clock generators.
- KSP Keywords
- Detection Method, Fault detection method, clock domain, clock generator, defect detector, driving voltage, fault detection, power supply
- Family
| Status | Patent | Country | KIPRIS |
|---|---|---|---|
| Registered | PROCESSOR SYSTEM AND FAULT DETECTION METHOD THEREOF | KOREA | KIPRIS |