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Detail
Registered MULTI-CORE PROCESSOR AND CACHE MANAGEMENT METHOD THEREOF
- Inventors
- Han Jin Ho, Kwon Young-Su
- Application No.
- 15832862 (2017.12.06)
- Publication No.
- 20180157549 (2018.06.07)
- Registration No.
- 10740167 (2020.08.11)
- Country
- UNITED STATES
- Project Code
- 16PB2300, Automotive ECU SoC and Embedded SW for Multi-domain Integration, Kwon Young-Su
- Abstract
- A multi-core processor connected to main memory or peripheral device and having dual modular redundancy mode in which each processor performs the same task includes a first processor which generates first write-in data by performing the task, and writes the first write-in data to the main memory or peripheral device after fault detection operation on the first write-in data, a second processor which generates second write-in data by performing the task, and prevents writing of the second write-in data to the main memory or peripheral device after the fault detection operation on the second write-in data, and a fault manager which performs the fault detection operation by comparing the first write-in data with the second write-in data in the mode, wherein the first write-in data is written to the main memory using first data cache, which is managed using dirty bit indicating whether to synchronize with the main memory.
- Family
| Status | Patent | Country | KIPRIS |
|---|---|---|---|
| Registered | MULTI-CORE PROCESSOR AND CACHE MANAGEMENT METHOD THEREOF | KOREA | KIPRIS |