상세정보
등록 가변적인 이중화 기능을 갖는 캐시 메모리 및 이를 포함하는 프로세서
- 출원번호
- 15832862 (2017.12.06)
- 공개번호
- 20180157549 (2018.06.07)
- 등록번호
- 10740167 (2020.08.11)
- 출원국
- 미국
- 협약과제
- 16PB2300, Multi-domain 자동차 전장 구조를 위한 ECU용 SoC 및 임베디드 SW 개발, 권영수
- 초록
- A multi-core processor connected to main memory or peripheral device and having dual modular redundancy mode in which each processor performs the same task includes a first processor which generates first write-in data by performing the task, and writes the first write-in data to the main memory or peripheral device after fault detection operation on the first write-in data, a second processor which generates second write-in data by performing the task, and prevents writing of the second write-in data to the main memory or peripheral device after the fault detection operation on the second write-in data, and a fault manager which performs the fault detection operation by comparing the first write-in data with the second write-in data in the mode, wherein the first write-in data is written to the main memory using first data cache, which is managed using dirty bit indicating whether to synchronize with the main memory.
- 패밀리
| 구분 | 특허 | 출원국 | KIPRIS |
|---|---|---|---|
| 등록 | 멀티 코어 프로세서 및 그것의 캐시 관리 방법 | 대한민국 | KIPRIS |