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Detail
Registered MULTI-CORE PROCESSOR AND OPERATION METHOD THEREOF
- Inventors
- Han Jin Ho, Shin Kyoung Seon, Kwon Young-Su
- Application No.
- 15832824 (2017.12.06)
- Publication No.
- 20180165246 (2018.06.14)
- Registration No.
- 10642782 (2020.05.05)
- Country
- UNITED STATES
- Project Code
- 16PB2700, Robust Fault-Resilient SW for Vehicle Processors, Kwon Young-Su
- Abstract
- A multi-core processor having a first operation mode in which processors perform the same task and a second operation mode in which the processors perform different tasks includes first and second processors configured to write an operation mode value to a first register or second register when a function called in executed software requests the first or second operation mode, a manager configured to assign core IDs of the first and second processors according to the operation mode value stored in the first register or second register, and a reset controller configured to reset the first and second processors in response to the function, wherein the manager assigns the same core ID to the first and second processors when the operation mode value indicates the first operation mode, and allocates different core IDs to the first and second processors when the operation mode value indicates the second operation mode.
- Family
| Status | Patent | Country | KIPRIS |
|---|---|---|---|
| Registered | 멀티 코어 프로세서 및 그것의 동작 방법 | KOREA | KIPRIS |