Registered
GENERAL PURPOSE COMPUTING ACCELERATOR AND OPERATION METHOD THEREOF
- Inventors
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Jeongmin Yang, Kwon Young-Su, Han Jin Ho
- Application No.
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17446678 (2021.09.01)
- Publication No.
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20220147353 (2022.05.12)
- Registration No.
- 11775303 (2023.10.03)
- Country
- UNITED STATES
- Project Code
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20JS2100, Supercomuter CPU Processor Research and Development based-on Open ISA,
Han Jin Ho
- Abstract
- Disclosed is a general-purpose computing accelerator which includes a memory including an instruction cache, a first executing unit performing a first computation operation, a second executing unit performing a second computation operation, an instruction fetching unit fetching an instruction stored in the instruction cache, a decoding unit that decodes the instruction, and a state control unit controlling a path of the instruction depending on an operation state of the second executing unit. The decoding unit provides the instruction to the first executing unit when the instruction is of a first type and provides the instruction to the state control unit when the instruction is of a second type. Depending on the operation state of the second executing unit, the state control unit provides the instruction of the second type to the second executing unit or stores the instruction of the second type as a register file in the memory.
- KSP Keywords
- AND operation, Control Unit, General purpose computing, Operation method, Register file, instruction cache, operation state, state control
- Family
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