20kbps급 영상 신호, 압축 복원 VLSI, 6kbps급 음성 신호, 통합 VLSI 설계
Funding Org.
정보통신부
Research Org.
한국전자통신연구원
Project Code
98MM1700, Research on Low Power Video Processor,
Cha Jin Jong
Abstract
o H.263 영상신호 압축복원 VLSI 설계 - 지원 영상 형식 : Sub-QCIF(128x96), QCIF(176x144), CIF(352x288), - 영상 처리 성능 : 최대 QCIF25 프레임/초 - 출력 비트율 : 16∼24kbit/s - 회로 규모 : 약 125만 트랜지스터(114,100 논리 게이트, 30k 비트 SRAM) - 클럭 주파수 : 33MHz o G.723 음성신호 압축복원 VLSI 설계 - G.723 보코더 알고리즘의 어셈블리 프로그램 : 총 24,500 라인 - DSP 코어 : 16비트 고정 소수점 연산 방식 - DSP 코어 성능 : 최대 40MIPS at 3.3V - DSP 코어 회로 규모 : 약 160만 트랜지스터 (28,230 논리 게이트) - DSP 내장 프로그램 메모리 : 16kx24 비트 ROM - DSP 내장 데이터 메모리 : 10kx16 비트 ROM, 3kx16 비트 SRAM - DSP 코어 면적 : 3.25mmx4.76mm o 영상 및 음성 신호 압축복원 통합 VLSI 설계 - 회로 규모 : 약 285만 트랜지스터 (142,300 논리 게이트) - 칩 면적 : 9.02mmx9.06mm - 전원전압 : 3.3V - 소비전력 : 0.75W(예상) - 패키지 : 208핀 QFP - 공정기술 : 3.3V, 0.5um 3충배선 CMOS 공정기술
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