ETRI-Knowledge Sharing Plaform

Ultra-Low Power(ULP) Spiking Neural Networks Human Body Communication(HBC) Field-Programmable Gate Array(FPGA) The Body Internet Of Things(IoT) Body Channel Edge Computing Video Codec High Performance Energy-Efficient Power Saving Voltage Level Network On Chip(NoC) Wearable Devices Iot Devices Artificial Intelligent Performance Evaluation Ultra High Definition Multi-Core Processor Signal Transmission Bit Error Rate Fault-Resilient Temperature Effect Inversion(TEI) Low Power Consumption Wireless Body Area Network Voltage Converter Cmos Process Electric Signal Event-Driven Very Large-Scale Integration(VLSI) Multi-Domain Biometric Features Instruction Sets Body Posture Fully Depleted Silicon On Insulator(FD SOI) Low Power Processor Multi-Core Platform Platform Technology Transmission Medium Capacitor Charging User Recognition Hardware Implementation Soi Technology Rapid Prototyping Technology Battery-Powered Processor Architecture Current-Mode(CM) Support Vectormachine(SVM) Creative Technology Simd Architecture Multicore Architecture Full-Custom Smart Devices Capacitive Coupling Multi-Standard Video Decoding Design Methodology 28nm Fd-Soi Switched Capacitor(SC) Processor Design Channel Characteristics Classification Accuracy Domain Integration Virtual Platform Fpga Prototype Path Loss Performance Degradation Video Compression Integrated Architecture Root-Mean-Square Delay Spread Transmission Channel Energy Loss Training And Testing Voltage Scaling Design Exploration Capacitor Voltage Transmitter And Receiver High Energy Efficiency Measurement And Analysis Floating Point Unit Test Structures Measurement Results Performance Analysis Fpga Device Instruction Set Architecture Chirp Signals Hardware Complexity Load Current Inter Symbol Interference(ISI) Ultra-Low-Energy Machine Learning Algorithms Memory Storage Active Period Active Devices Asynchronous Interface Wireless Technologies Measurement Setup Circuit-Based Analog Circuits Intellectual Property(IP) Mpeg-4 Energy Harvester Fake Fingerprint High Data Rate Increasing Temperature Interface Circuit Rate Performance Spoof Detection Open Source Highly Reliable Maximum Data Rate Experimental Setup Functional Verification Sensor Applications Massively Parallel Wide Range Big-Data Current Trends Vector Processor Application-Specific Instruction Set Processor Classification Performance Specific Applications Commercial Products Clock Frequency Detection Probability Anti-Spoofing Data Transmission Simulation Results Floating-Point Operations Bio-Signal Acquisition Convolution Neural Network(CNN) Arm Processor Energy Saving MPEG-2 Biologically Inspired Energy-Aware Iterative Algorithms Lock Time Mean Square Error(MSE) Network Processing Operating Efficiency Signal-To-Noise Wearable Electronic Device Architecture Design Capacitor Array Control Signal Generation K-Nearest Neighbors (Knn) Algorithm Load Conditions State University Decision Boundary In-Depth Analysis Noc Simulator Parallel Connection Temperature Characteristics Soc Architecture Dynamic Voltage Effectiveness Evaluation Mobile Services Quad-Core Processor System Development Video Surveillance System Fixed Point Fifth Generation (5g) Cellular Fully-Connected Register Transfer Level Signal Noise Ratio(SNR) VC-1 Transmission Section 60 Ghz Starting Point Biometric System Carrier-To-Noise Ratio(CNR) Electrical Power Function Module Multiple Channels Network Applications Practical Design Vliw Processor System-Level Virtualization Principal Component Analysis (Pca) Dispersive Effect Electrical Charging Fully Integrated Fingerprint Recognition Hardware And Software Platform Signal Detection Wavelet Features Ultra-Lightweight Biometric Signals Configurable Processor Inline Assembly Membrane Capacitor One-Class Svm Peak Efficiency Small-Sized System Reliability Low Supply Voltage Software Development Kit Complementary Metal-Oxide-Semiconductor(CMOS) Channel Modeling Energy Recycling Experimental Result Frame Detection Input Voltage Spin-Torque Transfer Raw Data Anomaly Detection System Duty Ratio End Module Multi-Pipeline Power Range Simulation Framework Supply Power Variable Precision Digital Controller 5g Millimeter-Wave Bulk Cmos Chip Architecture Computing Resources Electric Power Head-Mounted Image Processing(IP) Mobile System Platform Architecture Semiconductor Manufacturing Knowledge Distillation Multi-Source Non-Uniform Neural Network Simulation Output Voltage Ripple Parallel Decoding Ap Soc Computationally Expensive Performance Prediction Multiple Interfaces Channel Analysis Feasibility Study Hardware Accelerator Modulation Method Power Allocation(PA) Amplitude Variation Gradient Descent Multi-Level Radio-Frequency Synchronization Algorithm Current Error High Resolution Images Learning Methods Self-Power Limited Lifetime Large Memory Open Circuit Voltage(OCV) Potential Energy Spike Transmission Wide Band Electric Energy Fast Motion Fingerprint Biometrics Hodgkin-Huxley Neuron Model Ni Foil System Design Compressed Domain Design Requirements Domain Analysis Motion Detection Frequency Shift Weight Accumulation Top-Down Analog Front-End Biological Behavior Biological Characteristics Data Capacity Huge Data Virtual Model All-To-All Wide Dynamic Range Average Energy Consumption Augmented Reality(AR) Capacitor Bank Channel Measurement Development Time Double Date Rate Large Network Post-Fabrication Video Decoder Fpga Prototyping Integrated Circuit(IC) Thermoelectric Effects Shared Memory Beta Source Cache Coherence Digital Signal Processing Formula Presented Maximum Likelihood (Ml) Detector Embedded Software Fpga Board Matching Network Multi-Chip Transceiver Design System-Level Design Core Chip External Control High Bandwidth Memory(HBM) Memory Contention Real-Time Constraints State-Of-The-Art Sampling Offset 48 V Adaptive Filter Body Biasing Compressed Images Down-Chirp High-Speed Wireless Hardware Module Human Recognition Narrow-Band Test Data Time Average Wireless Link Communication Overhead Biometric Recognition Circuit Implementation Dc Voltage Embedded Ai Neural System Nano Second Phase Inversion Voltage Drop Test Circuit Ai Applications Circuit Simulation Continuous Phase Leaky Integrate-And-Fire Multiple Media Process Level Wide Load Range 5 Nm Address-Event-Representation Challenging Issues Development Cost Frequency Scaling Feature Vector Modular Structure Custom Instructions Impulse Response Measurement Keyword Spotting Low Noise Multi-Channel Memory Bottleneck Random Variations Mapping Method Accelerator Architecture Filter Approach High Efficiency Mmu-Less Embedded Systems Minimum Redundancy Maximum Relevance Resource-Constrained Signal Processing Techniques Short-Circuit Current Single-Precision Total Power Detection Systems(IDS) Xilinx Virtex Adverse Effects Crossbar Array Cross-Layer Optimization Low Power Design Maximum Efficiency Network Architecture Search Method 130 Nm Energy Converter Feature Extraction Industrial Applications Network Configuration Queue Stability Receive Filter Signal Processing Module Unsupervised Anomaly Detection Conventional Energy Design Guidelines Human Brain Low Power Analog Comprehensive Study Context Adaptive Clock And Data Recovery Electromagnetic Interference(EMI) Fingerprint Detection Global Clock Maximum Power Magnetic Random Access Memory Neuromorphic Systems Reconfigurable Structure Semiconductor Technology Single Core Speed-Up Storage Device Hard Real-Time On-Body Voltage Range Communication System Edge Devices Eda Tool Implantable Devices Measurement And Evaluation Need For Pipeline Processing Receiving Channel Series-Connected Dispersion Characteristics Frequency Selective Digital Transmission Frequency Range Network Parameters Operating Characteristic Curves Power Reduction Radiated Emission United States Variable Length Code Software Optimization Communication Performance Design Space Ieee Standards Labview Environment Large Amounts Of Data Silicon Carbide(3C-SiC) Development Trends Example-Based Electronic Design Automation Neural Network Training Parasitic Capacitance Stable Control Digital-To-Analog Converters End Nodes Offset Errors Performance Emulation Prototype Development Receiver Front-End Voltage Boosting Spike Timing Dependent Plasticity Conventional Methods Entropy Estimation Integrate-And-Fire Model Level Control Power Delay Profile(PDP) Transition Time Wearable Application Virtual Prototype Accelerator Design Baseline Profile Capsule Endoscopy Data Center Optimized Algorithms Power Efficiency Parallel Connected Receiver Operating Characteristic Specific Design Software Profiling Low Power System Mixed-Mode Off-Chip Power Management Next-Generation Sensor Data Analytics Analog Amplifier Cloud Computing Technology Design Architecture Environmental Variations Performance Loss Transfer Function(DTF) Second Transition Sinusoidal Wave Compression Ratio Delay Profiles Detection Method Feature Analysis Image Compression Load Circuit Optimum Load Phased Antenna Array 5g Cellular Networks Development Process Electric Device Minimizing Power Memory Management Unit Memory Bandwidth Power Generation True Random Number Generation Carry Out Charging Efficiency Charge Pump Object Region Power System-On-Chip Process Information Peak Detection Real-Time Anomaly Detection 100 Mhz Wireless Transmission Minimal Set Optimization Methods Processing Information Risc-V Instruction Set Signal Modulation Inter-Core Communication Charge Sharing(CS) Device Location Energy Harvesting(EH) Frequency Response Ip Video Handwritten Digits High Reliability Low-Power Operation Pilot Study Statistical Analysis Wireless Connection Data Traffic Energy Input Flexible Router Memory Footprint OC-SVM Process Technology Processing Speed Application Specific Processor Attenuation Effect Communication Reliability Measured Data Personal Privacy Positive Effects P-N Junction Path Gain Pre-Charge Selection Algorithm Unsupervised Training Application Development Electrode Size Feature Points Mnist Database Spike-Based Capsule Endoscope Consumption Energy Efficiency Of System Representative Feature Router Frequency Sensor Networks Writing Speed Coarse-Fine Electronic Devices Wire Congestion Spike-Frequency Adaptation Artificial Intelligence Models Dynamic Random-Access Memory(DRAM) Unique Characteristics Time Dispersion V Oc Case Studies Conventional Test Design Environment Detection Features Energy Reduction Electrode Surface Multicore Baseband Point Model Security System Automatic Control Design Verification Electric Circuit Model Hardware Architecture Inter-Chip Communication Design Parameters Driving Characteristics High-Precision Mobile Virtual Reality Model-Based Power Source Rapid Development Systems-On-Chip SP800-90B Adaptive Algorithm Deep Sea Hardware Structure Interference Effect Maximum Accuracy On-Chip Infrastructure Threshold Range Approximate Computation Anomaly Detection Algorithm Dc-Dc Converters FDSOI CMOS Single-Stage Settling Time Stored Energy Various Approaches Time Based Xilinx Fpga Charging Method Energy Management Circuit Energy Conversion Experiment Results Frequency Calibration Image Data Minimum Entropy Operating Frequency Power Performance Resource Utilisation Signal Attenuation Virtualized System Level Of Training Mixed-Signal Circuit Detection Accuracy Signal Distortion Spoofing Attack