ETRI-Knowledge Sharing Plaform

Xilinx Virtex Haar-Like Features Fpga Implementation Turbo Decoder Data Services(DSs) Face Detection Max-Log-Map Algorithm Experimental Result Spiking Neural Networks Performance Evaluation Virtual Platform Active Devices Face Recognition Systems Human Body Communication(HBC) Asynchronous Interface Interface Circuit Creative Technology Real-Time Application Baseband Receiver Low-Power Transceiver Design Architecture Design Analog Circuits Body Channel Broadcasting Services Coding Gain Correction System Crossbar Array Detection Probability Eye Detection Frame Detection Highly Reliable Hardware Architecture Illumination Invariant Multimedia Data Multi-Pipeline System Design Spike Transmission Power Consumption Channel Characteristics Clock And Data Recovery IMT-2000 Implantable Devices Transmission Medium Backward Compatibility Hardware Model Heterogeneous Feature Iterative Decoder Low Supply Voltage Modulation Scheme Modulation Method Power Dissipation Path Loss Quasi-Cyclic Low-Density Parity-Check(QC-LDPC) Viterbi Decoder Root-Mean-Square Delay Spread The Body Address-Event-Representation Bio-Signal Acquisition Comprehensive Study Discrete Cosine Transform Design Architecture Experimental Setup Hardware And Software Hodgkin-Huxley Neuron Model Integrity Verification Measurement And Evaluation Maximum Data Rate Signal Generation Self-Quotient Image Point Model Path Gain Pipeline Processing Analog Front-End Body Posture Battery-Powered Cascaded Classifier Core Chip Design And Implementation Dispersive Effect Enhanced Data Rate Feature Extraction High Energy Efficiency Inter-Chip Communication Linear Discriminant Analysis(LDA) Sensor Networks Signal Modulation Performance Degradation 28 Nm Symbol Mapping Channel Modeling Development Environment Digital Transmission Floating Point Hardware System Illumination Effect Lock Time Application Software Operating System Signal Processing Module Receiver Front-End Communication System Challenging Issues Digital Multimedia Broadcasting Digital Signal Processing Electric Signal End Module Full-Custom High Reliability Mobile Multimedia Signal Transmission Phase Inversion Time Duration Transmitter And Receiver Bit Error Rate(And BER) Broadband Communication Error Correction Hw-Sw Codesign Hierarchical Modulation Hardware Implementation System Reliability Verification Module Transaction Level Model