ETRI-Knowledge Sharing Plaform

Haar-Like Features Turbo Decoder Fpga Implementation Xilinx Virtex Data Services(DSs) Face Detection Max-Log-Map Algorithm Performance Evaluation Spiking Neural Networks Experimental Result Virtual Platform Active Devices Face Recognition Systems Human Body Communication(HBC) Asynchronous Interface Interface Circuit Creative Technology Low-Power Baseband Receiver Real-Time Application Analog Circuits Architecture Design Broadcasting Services Correction System Coding Gain Crossbar Array Detection Probability Power Consumption Transceiver Design System Design Spike Transmission Eye Detection Frame Detection Hardware Architecture Illumination Invariant Highly Reliable Multimedia Data Multi-Pipeline Body Channel Clock And Data Recovery Channel Characteristics IMT-2000 Implantable Devices Backward Compatibility Path Loss Power Dissipation Viterbi Decoder Quasi-Cyclic Low-Density Parity-Check(QC-LDPC) Transmission Medium Hardware Model Heterogeneous Feature Iterative Decoder Low Supply Voltage Modulation Scheme Modulation Method Address-Event-Representation Bio-Signal Acquisition Comprehensive Study Discrete Cosine Transform Design Architecture Pipeline Processing Path Gain Point Model The Body Root-Mean-Square Delay Spread Signal Generation Self-Quotient Image Integrity Verification Experimental Setup Hardware And Software Hodgkin-Huxley Neuron Model Measurement And Evaluation Maximum Data Rate Analog Front-End Battery-Powered Body Posture Cascaded Classifier Core Chip Design And Implementation Dispersive Effect Performance Degradation Sensor Networks Signal Modulation 28 Nm Enhanced Data Rate Feature Extraction High Energy Efficiency Inter-Chip Communication Linear Discriminant Analysis(LDA) Channel Modeling Development Environment Digital Transmission Symbol Mapping Floating Point Hardware System Illumination Effect Lock Time Application Software Communication System Challenging Issues Digital Multimedia Broadcasting Digital Signal Processing Phase Inversion Signal Processing Module Receiver Front-End Signal Transmission Electric Signal End Module Full-Custom High Reliability Mobile Multimedia Operating System Bit Error Rate(And BER) Broadband Communication Verification Module Transmitter And Receiver Time Duration System Reliability Transaction Level Model Error Correction Hw-Sw Codesign Hierarchical Modulation Hardware Implementation