|
Conference
|
2024 |
A 6.4Gb/s/pin HBM3 Digital PHY with Low-Power, AreaEfficient Techniques for Chiplet-Based AI processors in 12-nm CMOS
Jaewoong Choi
Asian Solid-State Circuits Conference (A-SSCC) 2024, pp.1-3 |
|
|
|
Conference
|
2024 |
A Low-Power HBM3 Memory Interface
김이경
대한전자공학회 학술 대회 (하계) 2024, pp.1-2 |
|
|
|
Conference
|
2024 |
PetaScale High Performance PIM Processor Design using chiplet heterogeneous integration advanced package
한진호
대한전자공학회 학술 대회 (하계) 2024, pp.3375-3376 |
|
|
|
Conference
|
2024 |
Architecture for AI System on a Chip for Multiple NPU and High-Bandwidth Memory
김주엽
대한전자공학회 학술 대회 (하계) 2024, pp.3377-3379 |
|
|
|
Conference
|
2024 |
A Low-Power HBM3 Memory Interface
김이경
대한전자공학회 학술 대회 (하계) 2024, pp.3378-3379 |
|
|
|
Conference
|
2023 |
DQ and DQS Receiver for HBM3 Memory Interface with DFE Offset Calibration
Sujin Park
International SoC Design Conference (ISOCC) 2023, pp.215-216 |
0 |
|
|
Conference
|
2023 |
Chiplet Heterogeneous-Integration AI Processor
Youngsu Kwon
International Conference on Electronics, Information and Communication (ICEIC) 2023, pp.1-2 |
6 |
|
|
Conference
|
2022 |
8Gbps Data Receiver Design based on DFE for HBM3 Memory Interface
전영득
반도체공학회 학술 대회 (하계) 2022, pp.88-88 |
|
|
|
Conference
|
2022 |
Low Power All Digital Delay Locked Loop Circuit for Clock Delay Control Scheme per de-Skew Group of a HBM3 Memory Interface PHY
김이경
대한전자공학회 학술 대회 (하계) 2022, pp.525-526 |
|
|
|
Conference
|
2022 |
Design of high-speed memory data driving circuit with pre-emphasis function by using of output impedance control
조민형
대한전자공학회 학술 대회 (하계) 2022, pp.505-506 |
|
|
