ETRI-Knowledge Sharing Plaform

Mems Microphone Data Reuse Efficient Architecture Neural Processor Graphic Processing Unit(GPU) Control Method Artificial Intelligence Applications Conventional Methods Deep Neural Network(DNN) Network Accelerator Power Efficiency Support Vectormachine(SVM) Superior Performance 28 Nm Development Environment Reconfigurable Processor Development Time High Degree Image Stitching Cmos Process Computational Complexity Intellectual Property(IP) Acceleration Performance Multimedia Applications Memory Architecture Energy Loss Boost Mode Detection Distance Dual-Core Encoding Algorithm Electronic Systems High-Performance Computing Systems Heterogenous System Leakage Current Mode Change Moving Vehicle Output Buffer On-Chip Memory Power Saving State Machine Startup Mode Object Recognition Autonomous Vehicle Controller Area Network(CAN) Coupling Effects Energy Saving Encoding Technique Electronic Control Unit(ECU) Feedback Signal Front-End Execution Time Floating-Point Data Hardware Platform High-Dimensional Input Operation Image Recognition Lcd Display Motion Compensation(MoCo) Memory System Mesh Structure Max-Pooling Noise Performance Noise Filter Need For Optimization Analysis Processor Architecture Peak Efficiency Propagation Delay Reconfigurable Architecture Svm Algorithm Successive Approximation Analog-To-Digital Converter(SAR ADC) Single Instruction Multiple Data(SIMD) Two-Stage Tightly Coupled Vector Compression Video Sequences Weighted Sum User-Friendly Active Area Coupled With Deep Learning(DL) Frames Per Second(FPS) First Stage General-Purpose Graphics Processing Unit(GPGPU) Input Referred Noise In-Memory In-Vehicle Optimization Algorithm Panoramic Image Power Loss Minimization Potential Energy Quiescent Current Power Limit Power Model Road Vehicle Sensor Bias State-Of-The-Art Transformer-Based Technology Infrastructure Vehicle Safety Automated Optimization Cross-Coupled Dynamic Power Consumption Dynamic Voltage And Frequency Scaling Dynamic Frequency Scaling Energy Minimisation Embedded System Histograms Of Oriented Gradients(HOG) Higher Performance Inverse Quantization Infrastructure Support Linear Systems Large Memory Maximum Power Point Tracking(MPPT) Memory Structure Memory Access Scheduling Matrix Distribution Parallel Processor Quad-Core Synchronous Boost Converter Soc System Small Footprint Voltage Range 90 Nm Cmos Technology Area Constraints Bus Encoding Current Consumption Chip Area Design Verification Energy-Efficient Energy Consumption Function Call Homography-Based High Energy Efficiency High Efficiency Heterogeneous Systems High Snr Iso 26262 Mobile Application(APP) Matrix Multiplication Neural Network Applications Optical Flow Operating Frequency Open Technology Reference Current Run Time Real-Time Execution Soc Architecture Singular Value Decomposition(SVD) Stitching Method Shortest Path System-On-Chip Design Simd Processors Safety Requirements Voltage Booster Single Core Performance Evaluation Object Detection Best Performance Control Scheme Design Objective Estimated Performance Initial State Lbp Classifier Microphone Readout Multimedia Data Processing Maximum Output Power Multi-Dimensional Neural Processing Positive Feedback Probabilistic Information Process Technology Real-Time Image Power Behavior Static Power Wide Dynamic Range(WDR) Amplification Technique Autonomous Driving Vehicle Adaptive Power Cascade Structure Design Criteria Flexible Memory Functional Safety Fpga Board Graph Pattern Human Detection HOG-LBP Homogeneous Systems Input Voltage Inverse Transform Linear System Of Equations Local Binary Pattern Micro-Electro-Mechanical System(MEMS) Multiple Operating Modes Memory Banks Mobile Multimedia Operating Scheme Power Losses Programmable Control Power Down Readout Integrated Circuit Parameter Optimization Source Follower Speed-Up System Development Platform Safety Standard Software Implementation Voltage Scaling Wide Range 65nm Cmos 20 Hz Linear Transform Adaboost Classifier Audio And Video Bias Voltage Core Structure Compression Method Detection Algorithm High Speed High Frequency(HF) Integrated Approach Improved Performance Low Noise Low-Power Bus Lu Decomposition Low Input Motor Vehicles Memory-Efficient Output Voltage Power Supply Optimization Methods Pre-Emphasis Radial Basis Function Power Management Signal Amplification Self-Startup Single-Chip Silicon Area Voice Recognition 3 V Systolic Array