ETRI-Knowledge Sharing Plaform

Mems Microphone Neural Processor Efficient Architecture Data Reuse Graphic Processing Unit(GPU) Control Method 28 Nm Artificial Intelligence Applications Conventional Methods Deep Neural Network(DNN) Network Accelerator Power Efficiency Support Vectormachine(SVM) Superior Performance Development Environment Reconfigurable Processor Development Time High Degree Image Stitching Computational Complexity Cmos Process Intellectual Property(IP) Acceleration Performance Multimedia Applications Memory Architecture Energy Loss Moving Vehicle Boost Mode Detection Distance Dual-Core Encoding Algorithm Electronic Systems High-Performance Computing Systems Heterogenous System Leakage Current Mode Change Output Buffer Object Recognition On-Chip Memory Power Saving State Machine Startup Mode Floating-Point Data Autonomous Vehicle Controller Area Network(CAN) Coupling Effects Execution Time Energy Saving Encoding Technique Electronic Control Unit(ECU) Feedback Signal Front-End High-Dimensional Hardware Platform Input Operation Image Recognition Lcd Display Motion Compensation(MoCo) Memory System Mesh Structure Max-Pooling Need For Noise Performance Noise Filter Optimization Analysis Propagation Delay Peak Efficiency Processor Architecture Reconfigurable Architecture Svm Algorithm Successive Approximation Analog-To-Digital Converter(SAR ADC) Single Instruction Multiple Data(SIMD) Two-Stage Tightly Coupled User-Friendly Vector Compression Video Sequences Weighted Sum Active Area Coupled With Deep Learning(DL) Frames Per Second(FPS) First Stage General-Purpose Graphics Processing Unit(GPGPU) Input Referred Noise In-Memory In-Vehicle Optimization Algorithm Power Limit Power Model Panoramic Image Power Loss Minimization Potential Energy Quiescent Current Road Vehicle Sensor Bias State-Of-The-Art Transformer-Based Technology Infrastructure Vehicle Safety Automated Optimization Cross-Coupled Dynamic Voltage And Frequency Scaling Dynamic Frequency Scaling Dynamic Power Consumption Energy Minimisation Embedded System Histograms Of Oriented Gradients(HOG) Higher Performance Inverse Quantization Infrastructure Support Large Memory Linear Systems Memory Access Scheduling Maximum Power Point Tracking(MPPT) Memory Structure Matrix Distribution Parallel Processor Quad-Core Synchronous Boost Converter Small Footprint Soc System Voltage Range 90 Nm Cmos Technology Chip Area Open Technology Area Constraints Bus Encoding Current Consumption Design Verification Energy Consumption Energy-Efficient Function Call High Efficiency Homography-Based Heterogeneous Systems High Snr High Energy Efficiency Iso 26262 Matrix Multiplication Mobile Application(APP) Neural Network Applications Optical Flow Object Detection Operating Frequency Performance Evaluation Run Time Real-Time Execution Reference Current Stitching Method Single Core Singular Value Decomposition(SVD) Soc Architecture Shortest Path System-On-Chip Design Safety Requirements Simd Processors Voltage Booster Design Objective Best Performance Control Scheme Estimated Performance Initial State Lbp Classifier Microphone Readout Multimedia Data Processing Maximum Output Power Multi-Dimensional Neural Processing Power Behavior Probabilistic Information Positive Feedback Process Technology Real-Time Image Static Power Wide Dynamic Range(WDR) 65nm Cmos Homogeneous Systems 20 Hz Source Follower Multiple Operating Modes Autonomous Driving Vehicle Adaptive Power Amplification Technique Cascade Structure Design Criteria Functional Safety Fpga Board Flexible Memory Graph Pattern Human Detection HOG-LBP Input Voltage Inverse Transform Linear Transform Local Binary Pattern Linear System Of Equations Micro-Electro-Mechanical System(MEMS) Memory Banks Mobile Multimedia Operating Scheme Power Losses Power Down Programmable Control Parameter Optimization Readout Integrated Circuit Speed-Up System Development Platform Safety Standard Software Implementation Voltage Scaling Wide Range 3 V Optimization Methods Memory-Efficient Adaboost Classifier Audio And Video Bias Voltage Compression Method Core Structure Detection Algorithm High Speed High Frequency(HF) Improved Performance Integrated Approach Low Input Low Noise Low-Power Bus Motor Vehicles Lu Decomposition Output Voltage Power Management Power Supply Pre-Emphasis Radial Basis Function Signal Amplification Self-Startup Silicon Area Single-Chip Systolic Array Voice Recognition