ETRI-Knowledge Sharing Plaform

Digital Multimedia Broadcasting Low Power Consumption Turbo Decoder Convolution Neural Network(CNN) Artificial Intelligence Cmos Technology Data Services(DSs) Hardware Complexity Max-Log-Map Algorithm Design And Implementation Fft Processor H.264 Video Decoder Multimedia Decoding External Memory Single Chip Xilinx Virtex Thin Structure Neuromorphic Hardware Compression Method Cmos Process Discrete Fourier Transform Error Correction Fpga Implementation High Speed Viterbi Decoder Power Dissipation Fast Fourier Transform (Fft) Deep Learning(DL) MPEG-4 AVC Lte Uplink Need For Standard Cell Library Ultra-Thin Memristor Device Broadcasting Services Baseband Receiver Optical Ofdm Object Recognition Recognition Function Architecture Design Audio Data Coding Gain Correction System Design Aspects Data Transfer Data Compression High-Performance Computing Systems Heterogenous System Hardware Module Multimedia Applications Multimedia Data Memory Controller Number Of Layers Software Development Environment Modified Discrete Cosine Transform(MDCT) Twiddle Factor Access Method Next-Generation Optimization Analysis Rapid Growth Domain-Specific Hardware Interface High-Quality Image Recognition Intelligence Algorithm Ip-Based Long Term Evolution(LTE) Memory Access Maximum Throughput MPEG-2 TS Signal Integrity(SI) Inverse Fast Fourier Transform Pre-Coding Processing Unit Thermal Stability(TGA) Transformer-Based Abstract Syntax Tree And Operation A/V Synchronization Backward Compatibility Buffer Size Efficient Implementation Fixed-Point Iterative Decoder Internet Of Thing(IoT) Low-If Mixed-Radix Modulation Scheme National Standard State-Of-The-Art Multiplexing Of Data Weight Value Video Processing Source Coding Sampling Time(Ts) Array Structure Analog To Digital Converter(ADC) Basic Linear Algebra Subprograms Binary Weight Compression Efficiency Design Exploration Dedicated Software Eureka-147 Hardware And Software Higher Performance Input And Output Intermediate Representation Integration Architecture Large Memory Matrix Distribution Network Model Security System Linear Systems Single Carrier Frequency Division Multiple Access(SCFDMA) Power Optimization Visual Recognition Transport Stream(TS) And Frameworks Compression Algorithm Deep Neural Network(DNN) Data Explosion Dedicated Hardware Enhanced Data Rate Experimental Result Function Call Fast Computation Frequency Detection Heterogeneous Systems Micro-Processor Mobile Application(APP) Memory Management 100 Gb/S Large-Scale Peak Amplitude Power Ratio Performance Degradation Power Efficiency Xilinx Vivado 2015 System-On-Chip(SoC) Silicon Wafer Sampling Frequency Software Architecture Symbol Mapping Neural Processing Ofdm Systems Just-In-Time Best Performance Coherent Optical Orthogonal Frequency Division Multiplexing(CO-OFDM) Deep Convolutional Neural Networks Decoder Architecture Data Broadcasting Data Processing Error Recovery Fully-Connected Golomb-Rice Coding Lip Sync Machine Code Mean Absolute Error Radix-16 Small Form Factor Processor Performance 2.5d Interposers Xilinx Fpga Two-Dimensional(2D) Area-Efficient Operation Flow Pipelined Adc Total Power Baseband Chip Baseband Processor Computer Vision(CV) Communication System Channel Decoder Delay Time Graph Pattern Homogeneous Systems Heterogeneous Integration Linear System Of Equations Learning Application Lower Cost Mobile Multimedia Reference Model System Development Platform Lossless Compression Sample Data Parameter Optimization Wireless Multimedia Virtex-6 Vision Application Optimization Methods Time Duration Audio And Video Broadband Communication Caffe Framework Computing Resources Digital Audio Broadcasting Hardware Design Hierarchical Modulation Hardware Implementation Improved Performance Inference Engine Lu Decomposition Mnist Dataset Memory Bandwidth Radix-2 Reed-Solomon Decoder Software Framework Recognition Performance Fpga/Asic Implementation Physical Limitation Variable Length Coding