ETRI Knowledge Sharing Platform : Sujin Park

BROWSE

Researchers

연구자 검색
Keyword

Detail

Sujin Park Senior Researcher

Department: AI Sensing SoC Research Section

Contact

KSP Keywords: Heterogeneous Integration Duty Cycle(DC) Physical Layer High Speed Daisy Chain Design Aspects Higher Performance Line-By-Line Integration Architecture Single Chip 2.5d Interposers Thermal Stability Verification Method Die-To-Die Data Explosion High Bandwidth Memory(HBM) Pre-Emphasis Target Platform High Performance Low Power Offset Calibration Connection Area Artificial Intelligence Real-Time Processing Artificial Neural Network Integration Platform High-Density Next-Generation Physical Limitation Lower Cost Signal Integrity(SI) Large-Scale Data Decision Feedback Equalizer Cost Efficiency Operating Frequency Memory Interface Data Transfer Bonding Process Area-Efficient Architecture Design Ip-Based

Articles (14)
Patents (2)
Technology Transfer (0)
R&D Reports (0)
Standards (0)
Monographs/Talk (0)

논문 검색결과
Type	Year	Title	Cited
Conference	2025	Design of Driver Strength Calibration Circuit for Data Output Drivers in HBM3 Memory Interface 조민형 대한전자공학회 학술 대회 (하계) 2025, pp.1-2
Conference	2025	Design of an HBM3 Memory Interface Receiver with Integrated Offset Calibration Circuit 전영득 대한전자공학회 학술 대회 (하계) 2025, pp.1-2
Conference	2024	A 6.4Gb/s/pin HBM3 Digital PHY with Low-Power, Area Efficient Techniques for Chiplet-Based AI processors in 12-nm CMOS Jaewoong Choi Asian Solid-State Circuits Conference (A-SSCC) 2024, pp.1-3	0
Conference	2024	PetaScale High Performance PIM Processor Design using chiplet heterogeneous integration advanced package 최재웅 대한전자공학회 학술 대회 (하계) 2024, pp.3375-3376
Conference	2023	DQ and DQS Receiver for HBM3 Memory Interface with DFE Offset Calibration Sujin Park International SoC Design Conference (ISOCC) 2023, pp.215-216	0
Conference	2023	A Low Power Receiver using Dynamic Comparator of HBM3 Memory Interface 김이경 대한전자공학회 학술 대회 (하계) 2023, pp.220-221
Conference	2023	Design of Duty Cycle Monitor Circuit for Clock Signalusing in High-Speed DRAM 조민형 대한전자공학회 학술 대회 (하계) 2023, pp.190-191
Conference	2023	A Small-Area DFE Design Technique For HBM3 Memory Interface 전영득 대한전자공학회 학술 대회 (하계) 2023, pp.274-275
Conference	2023	2.5D Large-Scale Interposer Bonding Process Verification for PIM Heterogeneous Integration Platform 박수진 대한전자공학회 학술 대회 (하계) 2023, pp.213-214
Conference	2023	2.5D Large-Scale Interposer Bonding Process Verification using Daisy-Chain for PIM Heterogeneous Integration Platform Sujin Park International Conference on Electronics, Information and Communication (ICEIC) 2023, pp.1-3	0
Conference	2023	Chiplet Heterogeneous-Integration AI Processor Youngsu Kwon International Conference on Electronics, Information and Communication (ICEIC) 2023, pp.1-2	11
Conference	2022	8Gbps Data Receiver Design based on DFE for HBM3 Memory Interface 전영득 반도체공학회 학술 대회 (하계) 2022, pp.88-88
Conference	2022	Design of high-speed memory data driving circuit with pre-emphasis function by using of output impedance control 조민형 대한전자공학회 학술 대회 (하계) 2022, pp.505-506
Conference	2022	Low Power All Digital Delay Locked Loop Circuit for Clock Delay Control Scheme per de-Skew Group of a HBM3 Memory Interface PHY 김이경 대한전자공학회 학술 대회 (하계) 2022, pp.525-526

ETRI-Knowledge Sharing Plaform

BROWSE

Researchers

Detail

ETRI