ETRI-Knowledge Sharing Plaform

Video Codec Neural Processor Power Consumption Graphic Processing Unit(GPU) Motion Estimation(ME) Acceleration Performance Artificial Intelligence Applications Network Accelerator Power Efficiency 28 Nm Superior Performance Development Environment Development Time High Degree Software Implementation Mpeg-4 Video Intellectual Property(IP) Low-Power Data Reuse Single-Chip Multimedia Applications Electronic Systems Multi-Fpga On-Chip Memory Object Recognition Power Saving Video Coding Vlsi Implementation Energy Efficiency Electronic Control Unit(ECU) Execution Time Floating-Point Data Image Recognition Motion Compensation(MoCo) Mesh Structure Max-Pooling High Performance Processor Architecture Real-Time Video User-Friendly General-Purpose Graphics Processing Unit(GPGPU) Near Threshold Voltage Coupled With Cost-Effective Deep Learning(DL) In-Memory In-Vehicle Operating Temperature Power Limit Power Model Road Vehicle Vehicle Safety State-Of-The-Art Dynamic Frequency Scaling Clock Frequency Cmos Technology Discrete Cosine Transform Dynamic Voltage And Frequency Scaling Hardware And Software Higher Performance Processor Core Quantitative Analysis Quad-Core Rate Control Soc System Small Footprint Transient Faults Mobile Application(APP) Area Constraints Design Verification Neural Network Applications H.264 Video Decoder Iso 26262 Logic Gate Operating Frequency Real-Time Execution Run Time Software Architecture Video Formats Safety Requirements Single Point Estimated Performance Multi-Dimensional Neural Processing Error Resilience(ER) Error Concealment Process Technology Power Behavior Video System Fault-Tolerant Fault Injector Functional Safety Fpga Board Proposed Work Mobile Multimedia Maximum Frequency Autonomous Driving Vehicle Adaptive Power Coding And Decoding Pipeline Structure System-On-A-Chip Voltage Scaling Safety Standard Fault Injection Failure Rate Mobile Video Memory Architecture Bit Rate Computational Requirements H.264 Decoder High Speed Intra Refresh Power Management Voice Recognition Variable Length Coding Silicon Area Systolic Array