ETRI-Knowledge Sharing Plaform

Convolution Neural Network(CNN) High Performance Fpga Implementation Digital Multimedia Broadcasting Wireless-Powered Communication Network(WPCN) Xilinx Virtex Neuromorphic Hardware Artificial Intelligence Haar-Like Features Lte Uplink Cmos Technology Hardware Accelerator Turbo Decoder Low Latency Broadcasting Services Time Factor Energy Efficiency Optimization Multi-Antenna Real-Time Application Ultra-Thin Standard Cell Library MPEG-4 AVC Overall Design Fast Fourier Transform (Fft) Low-If Viterbi Decoder Optimization Problem Data Services(DSs) Face Detection Hardware And Software Hardware Complexity Latency Performance Low Power Consumption Max-Log-Map Algorithm Operating Frequency Design And Implementation Fft Processor H.264 Video Decoder Multimedia Decoding External Memory Virtual Platform Face Recognition Systems Single Chip Thin Structure Optimal Solution Compression Method Cmos Process Discrete Fourier Transform Error Correction Hardware Design Hardware Implementation Low Power Dissipation Memristor Device Baseband Receiver Optical Ofdm Object Recognition Research Institute Recognition Function Artificial Neural Network Coding Gain Correction System Compressed Images DVB-H Data Compression Eye Detection Filter Order Graphics Processing Hardware Module High Density Integration Illumination Invariant Multimedia Applications Multimedia Data Memory Controller Machine Learning Applications Number Of Layers Power Band User Throughput Twiddle Factor Successive Approximation Analog-To-Digital Converter(SAR ADC) Next-Generation Access Method Subthreshold Region Critical Path Computing Environment Elimination Method Graphic Processing Unit(GPU) Harvest-Then-Transmit Protocol High-Quality Logic Depth Large Vocabulary Long Term Evolution(LTE) Memory Access Maximum Throughput Need For Non-Convex Noise Figure(NF) Information And Communication Inverse Fast Fourier Transform Pre-Coding Wireless Powered Network Gain Control Transmission Scheme Allocation Scheme Backward Compatibility Buffer Size Fpga Device Finite Impulse Response (Fir) Filter Fixed-Point Hardware Model Heterogeneous Feature Iterative Decoder Internet Of Thing(IoT) Latency Time Mixed-Radix Modulation Scheme National Standard South Korea Multiplexing Of Data Speech Features Quasi-Cyclic Low-Density Parity-Check(QC-LDPC) Weight Value Video Processing Source Coding Time Allocation New Materials Sampling Time(Ts) Array Structure Binary Weight Common Subexpression Elimination Channel State Information(CSI) Compression Efficiency Design Exploration Doppler Effect Discrete Cosine Transform Eureka-147 Efficient Algorithms Frequency Error(FE) Filter Coefficients Generalized Structure Hidden Markov Model Integrity Verification Input And Output Large Memory Network Model Random Access Preamble Single Carrier Frequency Division Multiple Access(SCFDMA) Self-Quotient Image Physical Random Access Channel(PRACH) Power-Efficient Worst Case Visual Recognition 3GPP LTE Subthreshold Cmos Cascaded Classifier Compression Algorithm Dual Method Deep Neural Network(DNN) Dedicated Hardware Experimental Result Energy-Efficient Transmission Enhanced Data Rate Feature Extraction High Throughput(HTP) Iterative Algorithms Image Processing Logical Depth Linear Discriminant Analysis(LDA) Mobile Tv Micro-Processor Mobile Application(APP) 100 Gb/S Max-Min Large-Scale Peak Amplitude Power Ratio Performance Degradation Von Neumann Ultra-High Density Xilinx Vivado 2015 System-On-Chip(SoC) Silicon Wafer Software Architecture Tv Applications Symbol Mapping Automatic Speech Recognition(ASR) Ofdm Systems Cloud Computing Coherent Optical Orthogonal Frequency Division Multiplexing(CO-OFDM) Compression Ratio Detection Method Deep Convolutional Neural Networks Development Environment Decoder Architecture Data Broadcasting Fully-Connected Hardware System Golomb-Rice Coding Illumination Effect Multiple Constant Multiplication(MCM) Radix-16 Power Transmitter Power Allocation(PA) Preamble Detection Xilinx Fpga Two-Dimensional(2D) Time Performance Application Software Area-Efficient Operating System Object Region Operation Method Pipelined Adc Operation Flow Total Power Baseband Chip Baseband Processor CMOS RF Computer Vision(CV) Communication System Channel Decoder Delay Time Fpga Board Finite Impulse Response Filter(FIR filter) High Reliability Human Brain Information Transfer Image Compression Linux Device Driver Lagrange Dual Mobile Multimedia Remote Computing Reference Model Lossless Compression Sample Data Stand-Alone Power Delay Profile(PDP) Wireless Multimedia Virtex-6 Vision Application Time Duration Audio And Video Broadband Communication Control Range Cognitive Computing Continuous Speech Caffe Framework Computer Architecture Detection Latency Digital Audio Broadcasting Efficient Operation Hw-Sw Codesign High Speed Hierarchical Modulation Hybrid Mac Hardware Acceleration Low Power Analog Mnist Dataset Memory Bandwidth Radix-2 Resource Allocation(RA) Rf Front End Reed-Solomon Decoder Recognition Performance Fpga/Asic Implementation Simulation Results Parallel Processing Variable Length Coding Verification Module Transaction Level Model