ETRI-Knowledge Sharing Plaform

Spiking Neural Networks Human Body Communication(HBC) Wireless Body Area Network(WBAN) Body Area Networks(BANs) Body Channel Field Programmable Gate Arrays(FPGA) Signal Transmission The Body Low Power Consumption Electric Signal Body Posture Artificial Intelligence Channel Characteristics Path Loss Battery-Powered Wearable Device Rate Performance Interface Circuit Biometric Features Capacitive Coupling Detection Probability Frequency Selective Digital Transmission Highly Reliable Iot Devices Creative Technology Transmission Medium Internet Of Thing(IoT) Root-Mean-Square Delay Spread Bio-Signal Acquisition Transmission Channel Maximum Data Rate Ultralow Power(ULP) Support Vectormachine(SVM) Classification Accuracy High Data Rate Performance Evaluation Channel Modeling Energy Harvester Measurement And Analysis Active Devices Event-Driven Machine Learning Algorithms Measurement Setup Transmitter And Receiver Asynchronous Interface Inter-Symbol-Interference(ISI) Analog Circuits Specific Design Operating Mode One-Class Svm Transceiver Design Radio Frequency(RF) Artificial Neural Network Application Specific Biometric System Compressed Images Crossbar Array Distance Computation Data Traffic Design Methodology Energy Input Frame Synchronization Frame Detection Low-Complexity Massively Parallel Multi-Pipeline Raw Data Soi Technology System Design Spike Transmission Semiconductor Technology Pre-Processing Power Saving Processing Speed Practical Design Unique Characteristics Selection Algorithm Next-Generation Network Configuration Offset Errors Temperature Effect Inversion(TEI) Spoofing Attack Spoof Detection Biological Behavior Capsule Endoscope Cloud Computing Technology Convolution Neural Network(CNN) Communication Performance Clock And Data Recovery Electrode Surface Electrical Power Embedded Device Integrate-And-Fire Model High Resolution Image IEEE 802.15.6 Implantable Devices Large Amounts Of Data Mean Square Error(MSE) Nearest Neighbor(NN) Semiconductor Manufacturing Platform Architecture Processor Architecture Transmission Scheme Simplified Structure Test Data Transmission Method Unsupervised Anomaly Detection Network Applications Approximate Computation Brain-Inspired Biometric Recognition Channel Analysis Carrier-To-Noise Ratio(CNR) Electronic Devices Fixed-Point Integrated Circuit Minimum Redundancy Maximum Relevance Mnist Database Low Supply Voltage Measurement Method Modulation Method Resource Utilisation Peak Detection Voltage Drop Weight Accumulation Signal-To-Noise Signal Attenuation Accelerator Design Operating Characteristics Single-Precision Address-Event-Representation Channel Measurement Cyclic Redundancy Check(CRC) Clock Frequency Comprehensive Study Circuit-Based Detection Accuracy Down-Chirp Enabling Technologies Experimental Setup Frequency Calibration Handwritten Digit Hardware Accelerator Gradient Descent High-Bandwidth Memory Increasing Temperature Leaky Integrate-And-Fire Model-Based Memory Footprint Measurement And Evaluation Signal Generation Signal Detection Signal Distortion Storage Device Power-Efficient Path Gain Pipeline Processing Various Approaches Voltage Range Operating Frequency System-On-Chip(SoC) Training And Testing Receiver Operating Characteristic(ROC) Attenuation Effect Analog Front-End Capsule Endoscopy Complementary Metal-Oxide-Semiconductor(CMOS) Communication Reliability Core Chip Chip Area Digital Circuit Device Applications Dispersive Effect Energy-Efficient Experimental Result Fingerprint Recognition Electronic Design Automation(EDA) Future Development Frequency Range Image Data High Energy Efficiency Image Processing Impulse Response Measurement Iterative Algorithms Inter-Chip Communication Large-Scale Mixed Signal Market Trends Reliable Communication Simulation Framework Sensor Networks Signal Modulation Spin-Torque Transfer Power Performance Performance Loss Processing Information Performance Degradation Writing Speed Spectral Mask Signal Noise Ratio(SNR) Anti-Spoofing Anomaly Detection System Operating Characteristic Curves Operating Efficiency Sampling Offset Receive Filter Adaptive Filter Current Trends Compression Ratio Chirp Signals Computationally Expensive Intrusion Detection System(IDS) Data Capacity Double Date Rate Electrode Size Fake Fingerprint Floating Point Filter Approach Hamming Distance Lock Time Detection Method Neural Network Training Receiving Channel Power Range Personal Privacy Performance Prediction 3-Db Bandwidth Spectral Efficiency(SE) Wide Range Neuromorphic Circuits Network Processing Neuromorphic System Neural System Object Region OC-SVM Case Studies Signal Processing Module Transfer Function(DTF) Threshold Range Receiver Front-End Communication System Challenging Issues Development Process Design Guidelines Digital Signal Processing Dynamic Random-Access Memory(DRAM) Development Trends Delay Profiles Decision Boundary Electric Circuit Model Energy Management Circuit Edge Computing End Module Frequency Shift Full-Custom Image Compression Ieee Standards Measured Data Multi-Source Maximum Likelihood (Ml) Detector Phase Inversion Power Delay Profile(PDP) Process Information User Recognition Unsupervised Training Wearable Electronic Device Anomaly Detection Algorithm Neural Network Simulation Neuromorphic Hardware Output Voltage Transmission Section RISC-V Accelerator Architecture Computing Resources Classification Performance Design Requirements Device Location Design Parameters Data Transmission Efficient Architecture End Nodes Hardware Implementation Interference Effects Low Noise Magnetic Random Access Memory System Reliability Signal Processing Techniques Small-Sized Spike Timing Dependent Plasticity 48 V Principal Component Analysis (Pca) Variable Precision 28nm Fd-Soi 100 Mhz Switching Noise