ETRI-Knowledge Sharing Plaform

Distortion Ratio Active Area Spurious-Free Dynamic Range(SFDR) Small Area Successive Approximation Analog-To-Digital Converter(SAR ADC) Cmos Technology Supply Voltage Capacitor Array Chip Area Pipelined Adc High Speed Integral Nonlinearity Signal-To-Noise-And-Distortion Differential Nonlinearity(DNL) Sampling Frequency Clock Scheme Successive Approximation Register Analog-To-Digital Converter Ultra-Thin Single-Ended Low Drop-Out(LDO) First Stage Pipeline Adc Reduction Technique Effective Number Of Bits Low Power Consumption Operational Amplifiers(Op-Amps) Programmable Capacitor Variable Gain Amplifier(VGA) Flash Adc Power Reduction Signal Noise Ratio(SNR) A/D Converter Display Applications Flat Panel Display(FPD) High Linearity Reference Buffer Sampling Rate 65nm Cmos Dual-Channel Heterogeneous Integration Mems Microphone Micro-Electro-Mechanical System(MEMS) Source Follower Figure Of Merit Memristor Device Neuromorphic Hardware Pre-Emphasis Thin Structure Duty Cycle(DC) Artificial Neural Network Architecture Design Bonding Process Black-Out Design Aspects Data Transfer Flexible Design Multiplying Digital-To-Analog Converter(MDAC) Memory Interface Machine Learning Applications Output Buffer Object Recognition Offset Calibration Semiconductor Technology Autonomous Vehicle Artificial Intelligence Coupling Capacitor Controller Area Network(CAN) Clock Detector Driver Circuit Dynamic Biasing Feedback Signal Feedback Coefficient Hardware Platform High Power Ip-Based Noise Performance Noise Filter Operation Speed Pipelined Analog-To-Digital Converter Variable Resolution Signal Integrity(SI) Algorithmic Adc Deep Learning(DL) High-Resolution Input Referred Noise Level Converter(LC) Offset Cancellation Operation Flexibility Pipeline Stages Power Dissipation Vehicle Control Technology Infrastructure Thermal Stability(TGA) Sub-Sampling Sensor Interface Sensor Bias Sample-And-Hold Amplifier Circuit Design Decision Feedback Equalizer Flash-Sar Gain Range High Conversion High-Density Higher Performance Hardware Accelerator Input Signal Infrastructure Support Integration Architecture Pvt Variation Voltage Range Video Applications Wheel Speed Sensor Sampling Clock Scale-Down Signal Level Time Error 7 Mm Autonomous Driving Aperture Time Analog Front-End Area Reduction CAN BUS Current Consumption Complementary Metal-Oxide-Semiconductor(CMOS) Connection Area Cost Efficiency Digital-To-Analog Converters Digital Signal Design Techniques Daisy Chain Data Explosion Energy-Efficient Fully Differential Image Signal Processing Large-Scale Learning Algorithms Maximum Operating Frequency Operating Speed Performance Degradation Reference Current Voltage Booster Variation Tolerance Output Swing Switching Technique Real-Time Processing Open Technology Conversion Rate Clamp Circuit Common-Mode Voltage(CMV) Digital Core Full Scale Least Significant Bit(LSB) Ldo Regulator Microphone Readout Operational Transconductance Amplifier Positive Feedback Pipelined Sar Adc Power-Supply Rejection(PSR) Processing Platform Verification Method 2.5d Interposers Automotive Systems Amplification Technique Asynchronous Clock Capacitor Switching Common-Source Circuit Complexity Digital Calibration High-Bandwidth Integration Platform Line-By-Line Lower Cost Pre-Amplifier Readout Integrated Circuit Rejection Ratio User Interface Switched-Capacitor Circuit Sub-Adc Multi-Stage Amplifiers 20 Hz Single Chip 90-Nm Acquisition Time Amplifier Sharing Technique Bias Voltage Biasing Technique Distinct Sampling Die-To-Die Error Correction Fault Detection Scheme High Performance Computing Heterogeneous Computing Hybrid Mac Hardware Acceleration Low Power Analog Low Noise Low-Voltage Circuit Output Voltage Over-Current Protection Physical Limitation Target Platform 45-Nm Cmos Process Signal Amplification Settling Time