ETRI-Knowledge Sharing Plaform

Distortion Ratio Spurious-Free Dynamic Range(SFDR) Small Area High Performance Supply Voltage Pipelined Adc Capacitor Array Active Area Successive Approximation Analog-To-Digital Converter(SAR ADC) Cmos Technology Differential Nonlinearity(DNL) Signal-To-Noise-And-Distortion Chip Area Sampling Frequency Integral Nonlinearity Pre-Emphasis Thin Structure Successive Approximation Register Analog-To-Digital Converter Flash Adc Power Reduction Signal Noise Ratio(SNR) A/D Converter Display Applications Flat Panel Display(FPD) High Linearity Reference Buffer Dual-Channel Mems Microphone Source Follower 65nm Cmos Clock Scheme Figure Of Merit Reduction Technique Pipeline Adc First Stage Neuromorphic Hardware Single-Ended Memristor Device Programmable Capacitor Operational Amplifiers(Op-Amps) Low Power Consumption Effective Number Of Bits Low Drop-Out(LDO) Variable Gain Amplifier(VGA) Ultra-Thin Artificial Neural Network Bonding Process Black-Out Duty Cycle(DC) Flexible Design Memory Interface Multiplying Digital-To-Analog Converter(MDAC) Machine Learning Applications Output Buffer Offset Calibration Semiconductor Technology Autonomous Vehicle Coupling Capacitor Controller Area Network(CAN) Clock Detector Dynamic Biasing Feedback Signal Feedback Coefficient Hardware Platform High Power Noise Performance Noise Filter Operation Speed Pipelined Analog-To-Digital Converter Variable Resolution Algorithmic Adc High-Resolution Input Referred Noise Offset Cancellation Operation Flexibility Power Dissipation Pipeline Stages Sensor Bias Sub-Sampling Technology Infrastructure Circuit Design Flash-Sar Hardware Accelerator Gain Range Infrastructure Support Input Signal Sampling Clock Sample-And-Hold Amplifier Time Error 7 Mm Aperture Time Analog Front-End Area Reduction Current Consumption Complementary Metal-Oxide-Semiconductor(CMOS) Design Techniques Digital-To-Analog Converters Energy-Efficient Fully Differential Image Signal Processing Large-Scale Maximum Operating Frequency Operating Speed Open Technology Output Swing Performance Degradation Reference Current Switching Technique Voltage Booster Least Significant Bit(LSB) Ldo Regulator Microphone Readout Operational Transconductance Amplifier Positive Feedback Pipelined Sar Adc Processing Platform Sampling Rate Power-Supply Rejection(PSR) Amplification Technique Asynchronous Clock Capacitor Switching Circuit Complexity Common-Source Digital Calibration Heterogeneous Integration Integration Platform Micro-Electro-Mechanical System(MEMS) Multi-Stage Amplifiers Pre-Amplifier Readout Integrated Circuit Rejection Ratio Switched-Capacitor Circuit Sub-Adc 20 Hz 45-Nm Cmos Process 90-Nm Acquisition Time Amplifier Sharing Technique Bias Voltage Biasing Technique Distinct Sampling Error Correction High Speed Hybrid Mac Hardware Acceleration Low Noise Low-Voltage Circuit Low Power Analog Signal Amplification Settling Time