ETRI-Knowledge Sharing Plaform

Analog-To-Digital Converters(ADCs) Distortion Ratio Spurious-Free Dynamic Range(SFDR) Active Area Small Area Successive Approximation Analog-To-Digital Converter(SAR ADC) High Speed Capacitor Array Supply Voltage Chip Area Pipelined Adc Cmos Technology Signal-To-Noise-And-Distortion Differential Nonlinearity(DNL) Integral Nonlinearity Sampling Frequency High Linearity Low Drop-Out(LDO) Heterogeneous Integration Signal Noise Ratio(SNR) Programmable Capacitor 65nm Cmos Micro-Electro-Mechanical System(MEMS) Memristor Device Clock Scheme Flat Panel Display Single-Ended Pre-Emphasis Pipeline Adc Low Power Consumption Real-Time Processing Flash Adc Successive Approximation Register Analog-To-Digital Converter Artificial Neural Network Source Follower Figure Of Merit(FoM) Reduction Technique Power Reduction Dual-Channel Effective Number Of Bits(ENOB) Variable Gain Amplifier Thin Structure Neuromorphic Hardware Reference Buffer Duty Cycle(DC) Ultra-Thin First Stage A/D Converter Display Applications Mems Microphone Sampling Rate Noise Performance Coupling Capacitor Clock Detector Full-Scale High-Density Next-Generation Performance Degradation Switched-Capacitor Circuit Operational Amplifier High-Performance Computing(HPC) Physical Limitation Technology Infrastructure Biasing Technique Amplification Technique Capacitor Switching Distinct Sampling Rejection Ratio Switching Technique Energy-Efficient Lower Cost Pipelined Analog-To-Digital Converter Gain Range Operation Flexibility Signal Amplification Signal Integrity(SI) Digital Signal Multiplying Digital-To-Analog Converter(MDAC) Large-Scale Data Op-Amp Feedback Coefficient High Power Output Buffer Pvt Variation Decision Feedback Equalizer Noise Filters Time Error Flash-Sar Hardware Platform Circuit Complexity Cost Efficiency Vehicle Control Digital Core Power-Supply Rejection(PSR) Aperture Time Controller Area Network(CAN) Microphone Readout Offset Cancellation Settling Time Area-Efficient 7 Mm Video Applications Die-To-Die Data Explosion Level Converter Pipeline Stages High Bandwidth Memory(HBM) Maximum Operating Frequency Operating Speed Scale-Down Sub-Adc Target Platform Autonomous Vehicle Acquisition Time Readout Integrated Circuit Sensor Interface User Interface(UI) Least-Significant Bit(LSB) Infrastructure Support Automotive Systems Offset Calibration Sub-Sampling Image Signal Processing Positive Feedback Low Noise Connection Area Fully Differential Artificial Intelligence Output Voltage Digital Calibration Flexible Design Low Power Analog Pipelined Sar Adc Common-Source Circuit Design Semiconductor Technology Driver Circuit Voltage Range Common-Mode Voltage(CMV) Variation Tolerance Variable Resolution Asynchronous Clock Integration Platform Input Signal Output Swing High Resolution Processing Platform Signal Level Sampling Clock Feedback Signal Input Referred Noise Object Recognition Digital-To-Analog Converters Machine Learning Applications Operation Speed 20 Hz Ldo Regulator Architecture Design Ip-Based Multi-Stage Amplifiers Black-Out Bonding Process Memory Interface Physical Layer Sensor Bias Data Transfer Daisy Chain 90-Nm Design Aspects Fault Detection Scheme Higher Performance Sample-And-Hold Amplifier Operational Transconductance Amplifier(OTA) Design Techniques Line-By-Line CAN BUS Complementary Metal-Oxide-Semiconductor(CMOS) Integration Architecture Algorithmic Adc Deep Learning(DL) Current Consumption Single Chip Voltage Booster Clamp Circuit Dynamic Biasing Hardware Accelerator 2.5d Interposers Thermal Stability Autonomous Driving Hybrid Mac(HMAC) Reference Current Reference Generator Pre-Amplifier High Conversion Low-Voltage Circuit 45-Nm Cmos Process Heterogeneous Computing Verification Method Amplifier Sharing Technique Error Correction Learning Algorithm Wheel Speed Sensor Analog Front-End Power Dissipation Bias Voltage Hardware Acceleration Over-Current Protection Area Reduction Open Technology Conversion Rate