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Young-Deuk Jeon
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AI Sensing SoC Research Section
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Type Year Title Cited Download
Conference
2025 Design of an HBM3 Memory Interface Receiver with Integrated Offset Calibration Circuit   전영득   대한전자공학회 학술 대회 (하계) 2025, pp.1-2
Conference
2025 Design of Driver Strength Calibration Circuit for Data Output Drivers in HBM3 Memory Interface   조민형   대한전자공학회 학술 대회 (하계) 2025, pp.1-2
Conference
2025 A Chiplet Interface Incorporating Lane Repair Functionality for Differential Strobe Signals   김이경   대한전자공학회 학술 대회 (하계) 2025, pp.1-2
Conference
2024 A 6.4Gb/s/pin HBM3 Digital PHY with Low-Power, Area Efficient Techniques for Chiplet-Based AI processors in 12-nm CMOS   Jaewoong Choi   Asian Solid-State Circuits Conference (A-SSCC) 2024, pp.1-3 0
Conference
2024 Design of a Reference Generator for UWB Radar Receiver   조민형   대한전자공학회 학술 대회 (추계) 2024, pp.302-304
Conference
2024 Architecture for AI System on a Chip for Multiple NPU and High-Bandwidth Memory   김주엽   대한전자공학회 학술 대회 (하계) 2024, pp.3377-3379
Conference
2024 PetaScale High Performance PIM Processor Design using chiplet heterogeneous integration advanced package   최재웅   대한전자공학회 학술 대회 (하계) 2024, pp.3375-3376
Conference
2024 A Low-Power HBM3 Memory Interface   김이경   대한전자공학회 학술 대회 (하계) 2024, pp.1-2
Conference
2024 A Low-Power HBM3 Memory Interface   김이경   대한전자공학회 학술 대회 (하계) 2024, pp.3378-3379
Conference
2024 Background VREF calibration circuit design minimizing black-out time for Memory Interfaces   전영득   대한전자공학회 학술 대회 (하계) 2024, pp.357-358
Conference
2024 Design of 3.2GHz Write Strobe Clock Driver for HBM3 Memory Interface   조민형   대한전자공학회 학술 대회 (하계) 2024, pp.344-345
Conference
2023 DQ and DQS Receiver for HBM3 Memory Interface with DFE Offset Calibration   Sujin Park   International SoC Design Conference (ISOCC) 2023, pp.215-216 0
Conference
2023 2.5D Large-Scale Interposer Bonding Process Verification for PIM Heterogeneous Integration Platform   박수진   대한전자공학회 학술 대회 (하계) 2023, pp.213-214
Conference
2023 Design of Duty Cycle Monitor Circuit for Clock Signalusing in High-Speed DRAM   조민형   대한전자공학회 학술 대회 (하계) 2023, pp.190-191
Conference
2023 A Small-Area DFE Design Technique For HBM3 Memory Interface   전영득   대한전자공학회 학술 대회 (하계) 2023, pp.274-275
Conference
2023 A Low Power Receiver using Dynamic Comparator of HBM3 Memory Interface   김이경   대한전자공학회 학술 대회 (하계) 2023, pp.220-221
Conference
2023 Chiplet Heterogeneous-Integration AI Processor   Youngsu Kwon   International Conference on Electronics, Information and Communication (ICEIC) 2023, pp.1-2 11
Conference
2023 2.5D Large-Scale Interposer Bonding Process Verification using Daisy-Chain for PIM Heterogeneous Integration Platform   Sujin Park   International Conference on Electronics, Information and Communication (ICEIC) 2023, pp.1-3 0
Conference
2022 8Gbps Data Receiver Design based on DFE for HBM3 Memory Interface   전영득   반도체공학회 학술 대회 (하계) 2022, pp.88-88
Conference
2022 Design of high-speed memory data driving circuit with pre-emphasis function by using of output impedance control   조민형   대한전자공학회 학술 대회 (하계) 2022, pp.505-506
Conference
2022 Low Power All Digital Delay Locked Loop Circuit for Clock Delay Control Scheme per de-Skew Group of a HBM3 Memory Interface PHY   김이경   대한전자공학회 학술 대회 (하계) 2022, pp.525-526
Conference
2021 Design of ZQ Calibration circuit for high-speed LPDDR memory interface to improve signal integrity   조민형   대한전자공학회 학술 대회 (하계) 2021, pp.196-197
Conference
2021 Background VREF calibration circuit design for LPDDR5 Memory Interface   전영득   대한전자공학회 학술 대회 (하계) 2021, pp.194-195
Conference
2020 6.4Gb/s/pin PHY I/O Design   전영득   반도체공학회 학술 대회 2020, pp.1-1
Conference
2020 Design of LPDDR memory interface driver circuit with pre-emphasis function   조민형   대한전자공학회 학술 대회 (하계) 2020, pp.361-362
Conference
2020 Low-power and small-area 8Gbps data receiver design for LPDDR5 Memory Interface   전영득   대한전자공학회 학술 대회 (하계) 2020, pp.217-218
Conference
2019 DFE Design with Tunable Offset and Feedback Coefficient for Low-Power Memory Interface   전영득   대한전자공학회 학술 대회 (추계) 2019, pp.132-133
Conference
2019 Design of 0.5V Low Voltage-Swing Terminated Logic Driver for High-speed Memory Interface   조민형   대한전자공학회 학술 대회 (추계) 2019, pp.136-137
Conference
2019 Design of Analog and Digital Hybrid MAC Circuit for Artificial Neural Networks   Ki-Hyuk Park   International Conference on Electronics, Information and Communication (ICEIC) 2019, pp.621-623 3
Conference
2018 Design of Analog MAC Operation Circuit based on Current Source Synapse Cell for Neural Network Operation   조민형   대한전자공학회 학술 대회 (하계) 2018, pp.126-128
Conference
2018 SAR ADC with High-Accuracy Offset Control based on Capacitor Switching   전영득   대한전자공학회 학술 대회 (하계) 2018, pp.58-59
Conference
2018 A Heterogeneous and High Performance Driving Computing Hardware Platform for Autonomous Vehicles   Jung-Hee Suk   IEMEK Symposium on Embedded Technology (ISET) 2018, pp.1-2
Conference
2017 MAC Implementation based on Analog Circuit for CNN   전영득   대한전자공학회 종합 학술 대회 (추계) 2017, pp.222-223
Conference
2017 Driving Computing Hardware Platform for Autonomous Vehicles   석정희   한국통신학회 종합 학술 발표회 (하계) 2017, pp.285-285
Conference
2016 Analog Front-End Technique for 3D Motion Detection System based on IR LED   전영득   대한전자공학회 학술 대회 (추계) 2016, pp.1048-1049
Conference
2016 Real-Time Monitoring Technique for ADC of Automotive Applications   전영득   대한전자공학회 종합 학술 대회 (하계) 2016, pp.140-142
Journal
2016 Low-Noise MEMS Microphone Readout Integrated Circuit Using Positive Feedback Signal Amplification   Yi-Gyeong Kim   ETRI Journal, v.38, no.2, pp.235-243 5
Journal
2015 State-of-the-Art on Gesture Sensing Technology Based on Infrared Proximity Sensor   석정희   전자통신동향분석, v.30, no.6, pp.31-41
Conference
2015 Accurate Current-to-Voltage Conversion Technique of Wheel Speed Sensor Interface for Automotive ABS/ESC Analog SoC   김이경   대한전자공학회 종합 학술 대회 (하계) 2015, pp.1227-1229
Conference
2015 Design of High-Speed Controller Area Network Transceiver for Data Communication in Automotive System   조민형   대한전자공학회 종합 학술 대회 (하계) 2015, pp.1183-1186
Conference
2014 A 12bit 330MS/s Video DAC with High-Speed Asynchronous Digital Signal Level Converter   조민형   대한전자공학회 종합 학술 대회 (하계) 2014, pp.294-297
Conference
2014 SAR ADC Based on Input Switching Technique for Automotive Applications   전영득   대한전자공학회 종합 학술 대회 (하계) 2014, pp.11-12
Conference
2014 Over-Current Protection Technique with Improved Accuracy for Wheel Speed Sensor Interface of Automotive ABS/ESC Analog SoC   김이경   대한전자공학회 종합 학술 대회 (하계) 2014, pp.1969-1972
Journal
2013 ROIC Technology Trends for Sensors   노태문   전자통신동향분석, v.28, no.5, pp.83-92
Conference
2013 Multi-Sensor Signal Processing ROIC For Small-size Sensor Node   전영득   대한전자공학회 종합 학술 대회 (하계) 2013, pp.35-37
Conference
2013 Low Noise MEMS Microphone ROIC   김이경   대한전자공학회 종합 학술 대회 (하계) 2013, pp.1845-1846
Journal
2012 A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash–SAR Architecture   Young-Deuk Jeon   IEEE Transactions on Circuits and Systems II : Express Briefs, v.59, no.11, pp.741-745 17
Journal
2011 A 10-bit 30-MS/s Successive Approximation Register Analog-to-Digital Converter for Low-Power Sub-Sampling Applications   Young-Kyun Cho   Microelectronics Journal, v.42, no.12, pp.1335-1342 5
Conference
2011 A 12-bit 100-MS/s pipelined ADC in 45-nm CMOS   Jae-Won Nam   International SoC Design Conference (ISOCC) 2011, pp.405-407 5
Journal
2011 A 12-Bit 200-MS/s Pipelined A/D Converter with Sampling skew Reduction Technique   Jae-Won Nam   Microelectronics Journal, v.42, no.11, pp.1225-1230 1
Journal
2010 A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique   Young-Kyun Cho   IEEE Transactions on Circuits and Systems II : Express Briefs, v.57, no.7, pp.502-506 44
Conference
2010 A 9.15mW 0.22mm<sup>2</sup> 10b 204MS/s pipelined SAR ADC in 65nm CMOS   Young-Deuk Jeon   Custom Integrated Circuits Conference (CICC) 2010, pp.1-4 41
Journal
2009 A 1.2 V 12 b 60 MS/s CMOS Analog Front-End for Image Signal Processing Applications   Young Deuk Jeon   ETRI Journal, v.31, no.6, pp.717-724 5
Conference
2009 A 2.85mW 0.12mm2 1.0V 11-bit20-MS/s Algorithmic ADC in 65nm CMOS   Jae Won Nam   European Solid-State Circuits Conference (ESSCIRC) 2009, pp.468-471 6
Journal
2009 Switched-Capacitor Variable Gain Amplifier with Operational Amplifier Preset Technique   Young Kyun Cho   ETRI Journal, v.31, no.2, pp.234-236 1
Journal
2007 A 10-bit 205-MS/s 1.0- mm2 90-nm CMOS Pipeline ADC for Flat Panel Display Applications   Seung-Chul Lee   IEEE Journal of Solid-State Circuits, v.42, no.12, pp.2688-2695 52
Journal
2007 A 9-Bit 80-MS/s CMOS Pipelined Folding A/D Converter with an Offset Canceling Technique   Seung-Chul Lee   ETRI Journal, v.29, no.3, pp.408-410 6
Conference
2007 A 4.7mW 0.32mm2 10b 30MS/s Pipelined ADC Without a Front-End S/H in 90nm CMOS   Young-Deuk Jeon   International Solid-State Circuits Conference (ISSCC) 2007, pp.456-615 49
Conference
2007 A 10b 205MS/s 1mm2 90nm CMOS Pipeline ADC for Flat-Panel Display Applications   Seung-Chul Lee   International Solid-State Circuits Conference (ISSCC) 2007, pp.458-615 27
Conference
2006 A 5-mW 0.26-mm2 10-bit 20-MS/s Pipelined CMOS ADC with Multi-Stage Amplifier Sharing Technique   Young Deuk Jeon   European Solid-State Circuits Conference (ESSCIRC) 2006, pp.544-547 9