ETRI-Knowledge Sharing Plaform

Analog-To-Digital Converters(ADCs) Distortion Ratio Spurious-Free Dynamic Range(SFDR) Active Area Small Area Successive Approximation Analog-To-Digital Converter(SAR ADC) High Speed Capacitor Array Supply Voltage Chip Area Pipelined Adc Cmos Technology Signal-To-Noise-And-Distortion Differential Nonlinearity(DNL) Integral Nonlinearity Sampling Frequency Low Drop-Out(LDO) High Linearity Heterogeneous Integration Signal Noise Ratio(SNR) Programmable Capacitor 65nm Cmos Micro-Electro-Mechanical System(MEMS) Memristor Device Clock Scheme Flat Panel Display Single-Ended Pre-Emphasis Pipeline Adc Low Power Consumption Real-Time Processing Flash Adc Successive Approximation Register Analog-To-Digital Converter Artificial Neural Network Figure Of Merit(FoM) Source Follower Reduction Technique Power Reduction Dual-Channel Effective Number Of Bits(ENOB) Variable Gain Amplifier Thin Structure Neuromorphic Hardware Reference Buffer Duty Cycle(DC) Ultra-Thin First Stage A/D Converter Display Applications Mems Microphone Sampling Rate 20 Hz Coupling Capacitor Clock Detector Full-Scale High-Density Next-Generation Performance Degradation Switched-Capacitor Circuit Operational Amplifier High-Performance Computing(HPC) Physical Limitation Biasing Technique Technology Infrastructure Capacitor Switching Distinct Sampling Rejection Ratio Switching Technique Amplification Technique Energy-Efficient Lower Cost Pipelined Analog-To-Digital Converter Signal Integrity(SI) Gain Range Operation Flexibility Signal Amplification Digital Signal Multiplying Digital-To-Analog Converter(MDAC) Large-Scale Data Op-Amp Feedback Coefficient High Power Output Buffer Pvt Variation Decision Feedback Equalizer Noise Filters Flash-Sar Hardware Platform Time Error Vehicle Control Circuit Complexity Cost Efficiency Digital Core Power-Supply Rejection(PSR) Aperture Time Controller Area Network(CAN) Microphone Readout Offset Cancellation Settling Time Area-Efficient 7 Mm Conversion Rate Die-To-Die Data Explosion Level Converter Pipeline Stages High Bandwidth Memory(HBM) Maximum Operating Frequency Operating Speed Scale-Down Acquisition Time Autonomous Vehicle Readout Integrated Circuit Sensor Interface Sub-Adc Target Platform Infrastructure Support Least-Significant Bit(LSB) User Interface(UI) Automotive Systems Offset Calibration Sub-Sampling Image Signal Processing Low Noise Positive Feedback Connection Area Fully Differential Artificial Intelligence Output Voltage Digital Calibration Low Power Analog Pipelined Sar Adc Flexible Design Circuit Design Common-Source Semiconductor Technology Common-Mode Voltage(CMV) Driver Circuit Voltage Range Variation Tolerance Variable Resolution Asynchronous Clock Input Signal Integration Platform Output Swing High Resolution Processing Platform Sampling Clock Signal Level Feedback Signal Input Referred Noise Object Recognition Digital-To-Analog Converters Machine Learning Applications Operation Speed Noise Performance Ldo Regulator Architecture Design Ip-Based Multi-Stage Amplifiers Black-Out Bonding Process Data Transfer Memory Interface Physical Layer Sensor Bias Daisy Chain 90-Nm Design Aspects Fault Detection Scheme Higher Performance Sample-And-Hold Amplifier Operational Transconductance Amplifier(OTA) Design Techniques Line-By-Line CAN BUS Complementary Metal-Oxide-Semiconductor(CMOS) Integration Architecture Algorithmic Adc Deep Learning(DL) Single Chip Current Consumption Clamp Circuit Voltage Booster Dynamic Biasing Hardware Accelerator 2.5d Interposers Autonomous Driving Hybrid Mac(HMAC) Reference Current Thermal Stability Reference Generator High Conversion Low-Voltage Circuit Pre-Amplifier 45-Nm Cmos Process Verification Method Heterogeneous Computing Amplifier Sharing Technique Error Correction Learning Algorithm Wheel Speed Sensor Analog Front-End Power Dissipation Bias Voltage Hardware Acceleration Over-Current Protection Area Reduction Open Technology Video Applications