ETRI-Knowledge Sharing Plaform

Ultralow Power(ULP) Asynchronous Processor Asynchronous Circuits Power Consumption Functional Unit Pci-Express(PCIe) Cmos Technology Intelligent Vehicle Circuit Design Area Cost Encoding Scheme Instruction Sets National Defense Top-Down Design Delay-Insensitive Deep Submicron Layout Simulation Power-Efficient Processor Core Platform Development Processor Design Sensor Node Dual-Rail Design Flow Energy Consumption Global Interconnects Multiple-Valued Logic(MVL) Power Efficiency Risc Processor Current-Mode(CM) Dynamic Power Design Issues Design Approach Compound Semiconductor Encoder And Decoder Instruction Set Architecture Low Power Circuits Optical Communications Various Conditions Ubiquitous Computing Environment Fan-Out Handshake Protocol I/O Acceleration Global Clock Wire Length Design Technology Automated Algorithm Verification Model Timing Closure Power Saving On-Chip Components Technology Design Methodology Partial Removal Architectural Design Data Transfer