ETRI-Knowledge Sharing Plaform

Core/Shell Nanowires Ge/Si Core/Shell Directional Coupler(DC) Schottky Junction Spot Size Fabrication Process High Responsivity Integrated Circuit P-I-N Photodetectors Schottky Diode Slab Waveguide Silicon Wafer Low Dark Current 3-Db Bandwidth Strain Gradient Thin Film Resistor Ge Photodetectors High Speed Creative Technology Annealing Temperature Single Nanowire 2d Material Leaky Mode Reduced Pressure Chemical Vapor Deposition Vls Process Cross-Sectional Imaging Contact Size Annealing Conditions Base Structure Beam Profile Deposition Technique Doped Si Electrical Properties(I-V curve) Effective Power Focal Length Hole Carriers Key Parameters Anti-Stiction Coating Annealing Time N-Type Transistors Oxidation Of Silicon Photoelectric Characteristics Photonic Devices Pattern Analysis Process Conditions Reconfigurable Fet Selective Epitaxial Growth(SEG) Si Nanowires Transmission Electron Microscopy(TEM) Time Effect Waveguide Grating Coupler Crystal Plane Carrier Confinement Broadband Photodetector Epitaxial Layers Epitaxial Lateral Overgrowth Internal Photoemission Junction Formation Low Power Leakage 2d Semiconductors Wake-Up W Metal High-Quality 6 Ghz Minimum Gap Noise Performance Numerical Aperture Non-Volatile Memory(NVM) Novel Technique P-Type Silicon Separation Process Soi Process Ultra-High Performance Coupled Beam Absorption Edge Emitter Layer Electron Microscopy Analysis Eye Diagram Even Longer Wavelength Field-Effect Transistors(FETs) Highly Efficient Laser Light 5 Nm Metal Deposition Power Semiconductor Scanning Electron Microscopy(S.E.M.) Room-Temperature Rectifying Behavior Remnant Polarization Silicate Glasses Thermal Variation Tensile Strain Top Electrode Technology Forecasting Cut-Off Frequency Chemical Mechanical Polishing(CMP) Crystalline State Carrier Density Electronic Structures Forward And Reverse Glass Materials Hydrogen Silsesquioxane Intelligent Greenhouse Infrared Detector X-Ray Diffraction Analysis Model-Based Memory Applications Process Parameters Resistance Change Sulfurization Method Silicon-Based Surface Roughness Analysis Surface Potential Type-Ii Heterojunction Ultra-Thin Body(UTB) Ultra-High Vacuum Chemical Vapor Deposition Base Layer Building Block Energy Band Structure Gaussian Functions High Throughput(HTP) Ic Reliability Light Sources Limiting Factors Mid-Infrared(MIR) Operating Speed Prism Coupling Method Parameter Values Rf Performance Superior Performance Si Layer Silicon Epitaxial Layer System-On-Chip(SoC) Semiconductor Heterojunction Sound Performance Transition-Metal Dichalcogenides(TMDCs) Transit Time Techno-Economic Study Compact Model Charge Transport Amorphous Sio 2 Applied Bias Blue Laser Beam Propagation Method Device Size Density Change Electron Beam Lithography Heterojunction Bipolar Transistors(HBTs) Hybrid Electronics Heterojunction Barrier Initial State Maximum Oscillation Frequency N-Type Si Performance Tradeoffs Polarization Switching Reverse Bias Schottky Photodiode Single Wafer Silicon Electronics Window Size Active Devices Bulk Silicon Build-Up Time Diffraction Pattern Density Functional Theory(DFT) Electrical Characteristics Full Width Intensity Profile Highly Crystalline Heavily Doped Low Phase Noise Wide Range Optimal Conditions Optimized Process Potential Barrier Silicon-Germanium(SiGe) Output Coupling Resistance Variation Sige Hbt Silicon Device Transport Model Van Der Waals (Vdw) Heterostructures Waveguide Photodetector Current-Voltage Characteristics And Logic Gates Data Transmission Diffraction Limit Group Iv Ge-On-Si High Resistance High-Resolution X-Ray Diffraction Hexagonal Boron Nitride(h-BN) Low Noise Low-Cost Localized Oxidation Lithography Process Local Area 3.5 Ghz 1550 Nm 2.3 Ghz Minimum Noise Figure On-Chip Measurement Optical Devices Pulse Width Power Demand Silicon-On-Insulator (Soi) Technology