ETRI-Knowledge Sharing Plaform

Neural Network 28 Nm Single-Chip Low Power Consumption Neural Processor Cmos Process Digital Multimedia Broadcasting Multimedia Decoding Network Accelerator Power Efficiency Superior Performance Development Environment Development Time High Degree Intellectual Property(IP) H.264 Video Decoder Artificial Intelligence Applications Cmos Technology Fault Tolerance Processor Architecture MPEG-4 AVC Graphic Processing Unit(GPU) Acceleration Performance Standard Cell Library Data Reuse Audio Data Broadcasting Services Electronic Systems Multimedia Applications Object Recognition On-Chip Memory Power Saving Autonomous Cars Energy Efficiency Electronic Control Unit(ECU) Floating-Point Data High-Quality High Performance Image Recognition MPEG-2 TS Max-Pooling Mesh Structure User-Friendly Hardware Interface Vehicle Safety Video Processing Coupled With A/V Synchronization Deep Learning(DL) Efficient Implementation Electronics System Fixed-Point General-Purpose Graphics Processing Unit(GPGPU) In-Memory In-Vehicle Low-If Many-Core National Standard Power Dissipation Road Vehicle State-Of-The-Art Clock Frequency Analog To Digital Converter(ADC) Eureka-147 Higher Performance Quad-Core Sampling Time(Ts) Soc System Small Footprint Area Constraints Design Verification Fast Computation Frequency Detection High Throughput(HTP) Iso 26262 Memory Management Micro-Processor Mobile Application(APP) Operating Frequency Real-Time Execution Sampling Frequency Safety Requirements System-On-Chip(SoC) Silicon Wafer Self-Recovering Transport Stream(TS) Fault Performance Computing Performance Data Broadcasting Error Recovery External Memory Estimated Performance Lip Sync Multi-Dimensional Process Technology Safe Design Autonomous Driving Vehicle Adaptive Power Baseband Chip Baseband Processor Functional Safety Fpga Board Wireless Multimedia Pipelined Adc Software Implementation Total Power Safety Standard Voice Recognition Audio And Video Digital Audio Broadcasting Fpga/Asic Implementation High Speed Memory Bandwidth Memory Architecture Silicon Area Systolic Array Supply Voltage