ETRI-Knowledge Sharing Plaform

Neural Processor Video Codec Power Consumption Acceleration Performance Graphic Processing Unit(GPU) Motion Estimation(ME) Artificial Intelligence Applications 28 Nm Network Accelerator Power Efficiency Superior Performance Development Environment Development Time High Degree Software Implementation Intellectual Property(IP) Mpeg-4 Video Multimedia Applications Low-Power Single-Chip Data Reuse Video Coding Vlsi Implementation Electronic Systems Multi-Fpga Object Recognition On-Chip Memory Power Saving Execution Time Energy Efficiency Electronic Control Unit(ECU) Floating-Point Data High Performance Image Recognition Motion Compensation(MoCo) Max-Pooling Mesh Structure Processor Architecture Real-Time Video User-Friendly Vehicle Safety Cost-Effective Coupled With Deep Learning(DL) General-Purpose Graphics Processing Unit(GPGPU) In-Memory In-Vehicle Near Threshold Voltage Operating Temperature Power Limit Power Model Road Vehicle State-Of-The-Art Cmos Technology Clock Frequency Dynamic Frequency Scaling Discrete Cosine Transform Hardware And Software Higher Performance Dynamic Voltage And Frequency Scaling Quantitative Analysis Processor Core Quad-Core Rate Control Small Footprint Soc System Video Formats Area Constraints Design Verification H.264 Video Decoder Iso 26262 Logic Gate Mobile Application(APP) Neural Network Applications Operating Frequency Run Time Real-Time Execution Software Architecture Single Point Safety Requirements Transient Faults Video System Error Resilience(ER) Error Concealment Estimated Performance Multi-Dimensional Neural Processing Process Technology Power Behavior Voltage Scaling Coding And Decoding Autonomous Driving Vehicle Adaptive Power Fault-Tolerant Fault Injector Functional Safety Fpga Board Mobile Multimedia Maximum Frequency Pipeline Structure Proposed Work System-On-A-Chip Safety Standard Voice Recognition Variable Length Coding Computational Requirements Bit Rate Fault Injection Failure Rate H.264 Decoder High Speed Intra Refresh Mobile Video Memory Architecture Power Management Silicon Area Systolic Array