ETRI-Knowledge Sharing Plaform

Ge-On-Si Illumination Type High Responsivity Sige Hbt Type 1 Data Rate 3-Db Bandwidth Si Photodetector 50 GB 1550 Nm Data Transmission Bulk Silicon Bit Error Rate(And BER) Phase Shifter Cost-Effective Down-Conversion Mixer Reduced Pressure Chemical Vapor Deposition P-I-N Photodetectors 5.8 Ghz Low Dark Current Sige Film Optical Network Applications 2.4 Ghz Performance Levels Petri Net(PN) TO-CAN 6 Ghz High Sensitivity 1/F Noise Optical Interconnect(OI) Threading Dislocations(TDs) Zno Thin Films Field-Effect Transistors(FETs) Fabrication Process Optical Data Chemical Mechanical Polishing(CMP) Differential Drive Sige Alloy Reset Current Silicon Photonics Technology High Temperature Experimental Result Strained-Si Silicon Wafer Memory Device Silicon Substrate Sige Bicmos Technology Structure-Related Wide Range Dual-Channel Extinction Ratio Spiral Inductor Optical Transmission Silicon-Germanium(SiGe) P-Zno Ge Photodetectors Waveguide Photodetector Zno Films Low-Cost Bulk Cmos 40 Gb/S Photonic Devices Input Power In-Situ Annealing Ict Convergence Key Parameters Base Structure Bottom Electrode Cmos Compatible Process Cross-Sectional Imaging Concurrent Dual-Band Deposition Technique Dry Etching Electrical Properties(I-V curve) Memory Interface Novel Method Negative Differential Resistance(NDR) N-Type Transistors Practical Implementation Oxidation Of Silicon Phase Change Material(PCM) Parasitic Capacitance Prostate-Specific Antigen(PSA) P-N Junction Pattern Analysis Process Conditions Reconfigurable Fet Resonance Frequency Rf Isolation Switching Speed Semiconductor Technology Selective Epitaxial Growth(SEG) Threading Dislocation Density Time Effect Fowler-Nordheim (F-N) Stress Carrier Confinement High-Quality III-V I/O Devices Initialization Vector(IV) Insulator Material Low Concentration Annealing Temperature Au Nanoparticles(Au-NPs) Current-Voltage Creative Technology Driver Circuit Data Center Electrical Resistivity Energy Efficiency Epitaxial Lateral Overgrowth Electronic Chips Photonic Interconnects Low Power Leakage Mach-Zehnder (Mz) Modulator Medium Power Amplifier Non-Volatile Memory(NVM) Novel Technique Oxide Trap Density Operational Voltage Quality-Factor(Q-factor) Reverse Leakage Current Radio Link Structure Optimization Sige Epitaxial Growth Surface Immobilization Up-Conversion Mixer Crystal Plane Electronic-Photonic Integration Noise Performance P-Doped Rf-Magnetron Sputter Deposition Soi Process Higher Frequency Insertion Loss Integration Scheme Hole Concentration Hybrid Memory Cube Annealing Process Eye Diagram Etching Process Electrical Contact Network Communication Metal-Insulator Transition Oxidation Process Silicon Photonic Integrated Circuits Silicon Waveguide Situ Doping Signal-To-Noise Thermal Variation Thermal Stability(TGA) Tensile Strain Doped Poly-Si Polished Si Nano-Device Soi Wafer High Speed Network X-Ray Diffraction Analysis LOW POWER AND HIGH SPEED Buffer Layer Communication Applications Cut-Off Frequency External Quantum Efficiency Enhanced Performance Force Microscopy 1310 Nm Si Wafer Model-Based Nonreturn-To-Zero(NRZ) Surface Roughness Analysis Surface Potential Si Channel Top-Down Ultra-High Vacuum Chemical Vapor Deposition 65 Nm Heating Layers Crystalline State Carrier Density Silicon-Based Thin Films Ultra-Thin Body(UTB) High Speed Communication High Throughput(HTP) High Resistivity Ion Implantation Wire-Bonded Light Sources Building Block Current Consumption Cmos Driver Complementary Metal-Oxide-Semiconductor(CMOS) Quantum Channel 100 Gb/S Limiting Factors Monolithically Integrated New Method Optical Transceiver Operating Speed Phase Transition Rf Performance Silicon Epitaxial Layer System-On-Chip(SoC) Sound Performance Transit Time Coupled Waveguide 7 Mm Photonic Transceiver Hybrid Electronics Inp Hbt Avalanche Photodetector Amorphous Sio 2 Atomic Force Microscope(AFM) Applied Bias Conversion Gain Chalcogenide Alloys Compact Model Doped Silicon Density Change Fermi Level Maximum Oscillation Frequency Optical Communications Photonic Transmitter Photonic Integrated Circuits (Pics) Potential Applications On-Board Equipment P-N Heterojunction Power Amplifiers(PAs) P-Type Zno Performance Tradeoffs Process Technology Sige Source Single Channel Single Wafer Si-Cap Silicon Electronics Surface Analysis Travelling Wave Highly Doped Highly Crystalline High-Performance Computer(HPC) Window Size Key Role Low Phase Noise Low Voltage Build-Up Time Data Communication Diffraction Pattern 850 Nm Off-Chip Photonic Circuits Receiver Front-End Potential Barrier Front-End Circuit Optimized Process Germanium Photodetector Wavelength Range Joule Heating Interface Circuit High-Resolution X-Ray Diffraction 3.5 Ghz Low Noise Localized Oxidation Layer Growth And Logic Gates Cmos Receiver Cmos Front-End Cycling Endurance Data Computing Fully Integrated 2.3 Ghz Misfit Dislocation Local Area Modulation Efficiency Minimum Noise Figure Material Characteristics Sige Virtual Substrates Strain Relief Module Performance Optical Propagation Loss Optical Power On-Chip Measurement Optical Alignment Pulse Width Polycrystalline Silicon(poly-Si) Power Demand Rf Transmitter Relaxed Sige Small-Sized Single-Chip Second Metal Sige Bicmos Process Supply Voltage Silicon-On-Insulator (Soi) Technology Si Substrate Specific Binding Avalanche Breakdown Voltage Control Device Fowler-Nordheim Stress Sige Device