ETRI-Knowledge Sharing Plaform

Mems Microphone Neural Processor Data Reuse Efficient Architecture Graphic Processing Unit(GPU) Control Method Artificial Intelligence Applications 28 Nm Conventional Methods Deep Neural Network(DNN) Network Accelerator Power Efficiency Support Vectormachine(SVM) Superior Performance Development Environment Reconfigurable Processor Development Time High Degree Image Stitching Computational Complexity Cmos Process Intellectual Property(IP) Acceleration Performance Multimedia Applications Memory Architecture Energy Loss Boost Mode Detection Distance Dual-Core Encoding Algorithm High-Performance Computing Systems Heterogenous System Leakage Current Mode Change Moving Vehicle Output Buffer Object Recognition On-Chip Memory Power Saving State Machine Startup Mode Autonomous Vehicle Weighted Sum Two-Stage Tightly Coupled Vector Compression Video Sequences User-Friendly Controller Area Network(CAN) Coupling Effects Execution Time Energy Saving Encoding Technique Electronic Control Unit(ECU) Feedback Signal Front-End Floating-Point Data Hardware Platform High-Dimensional Input Operation Image Recognition Lcd Display Mesh Structure Max-Pooling Motion Compensation(MoCo) Memory System Noise Performance Noise Filter Need For Optimization Analysis Peak Efficiency Propagation Delay Processor Architecture Reconfigurable Architecture Successive Approximation Analog-To-Digital Converter(SAR ADC) Svm Algorithm Single Instruction Multiple Data(SIMD) Active Area Vehicle Safety Transformer-Based Potential Energy Optimization Algorithm Technology Infrastructure Coupled With Deep Learning(DL) First Stage Frames Per Second(FPS) General-Purpose Graphics Processing Unit(GPGPU) Input Referred Noise In-Memory In-Vehicle Power Limit Power Model Power Loss Minimization Quiescent Current Road Vehicle Sensor Bias State-Of-The-Art Automated Optimization Voltage Range Cross-Coupled Dynamic Voltage And Frequency Scaling Dynamic Frequency Scaling Dynamic Power Consumption Energy Minimisation Embedded System Electronic System Histograms Of Oriented Gradients(HOG) Higher Performance Inverse Quantization Infrastructure Support Large Memory Linear Systems Maximum Power Point Tracking(MPPT) Memory Access Scheduling Memory Structure Matrix Distribution Parallel Processor Quad-Core Synchronous Boost Converter Soc System Small Footprint Area Constraints Bus Encoding Voltage Booster Current Consumption Chip Area Design Verification Energy Consumption Energy-Efficient Function Call High Energy Efficiency High Efficiency Homography-Based High Snr Heterogeneous Systems Iso 26262 Optical Flow Object Detection Mobile Application(APP) Matrix Multiplication Neural Network Applications Open Technology Operating Frequency Performance Evaluation Reference Current Run Time Real-Time Execution Soc Architecture Singular Value Decomposition(SVD) Stitching Method Single Core Shortest Path 90 Nm Cmos Technology System-On-Chip Design Simd Processors Safety Requirements Wide Dynamic Range(WDR) Best Performance Control Scheme Design Objective Estimated Performance Initial State Lbp Classifier Microphone Readout Multimedia Data Processing Maximum Output Power Multi-Dimensional Neural Processing Power Behavior Positive Feedback Process Technology Probabilistic Information Real-Time Image Static Power Amplification Technique Autonomous Driving Vehicle Adaptive Power Wide Range 65nm Cmos Fpga Board 20 Hz Voltage Scaling Cascade Structure Design Criteria Functional Safety Flexible Memory Graph Pattern Human Detection HOG-LBP Homogeneous Systems Input Voltage Inverse Transform Linear Transform Linear System Of Equations Local Binary Pattern Micro-Electro-Mechanical System(MEMS) Multiple Operating Modes Memory Banks Mobile Multimedia Operating Scheme Power Losses Programmable Control Parameter Optimization Power Down Readout Integrated Circuit Source Follower Speed-Up System Development Platform Safety Standard Software Implementation Adaboost Classifier Audio And Video Voice Recognition 3 V Bias Voltage Core Structure Compression Method Detection Algorithm High Speed High Frequency(HF) Integrated Approach Improved Performance Lu Decomposition Low Noise Low-Power Bus Low Input Motor Vehicles Memory-Efficient Output Voltage Optimization Methods Pre-Emphasis Power Management Panoramic Images Power Supply Radial Basis Function Signal Amplification Self-Startup Single-Chip Silicon Area Systolic Array