ETRI-Knowledge Sharing Plaform

Ultralow Power(ULP) Field Programmable Gate Arrays(FPGA) Human Body Communication(HBC) Wearable Device Spiking Neural Networks Body Channel Internet Of Thing(IoT) Wireless Body Area Network(WBAN) The Body Voltage Level Body Area Networks(BANs) Signal Transmission Network On Chip(NoC) Power Saving Voltage Converter Temperature Effect Inversion(TEI) Low Power Consumption Body Posture RISC-V Sensor Networks Electric Signal Very Large Scale Integration(VLSI) Energy-Efficient Soi Technology Video Decoding Transmission Medium Path Loss Channel Measurement Capacitor Charging Multi-Core Platform Battery-Powered Multi-Standard Channel Modeling Switched Capacitor(SC) 28nm Fd-Soi Hardware Implementation Cmos Process Channel Characteristics Wide Range Voltage Scaling Classification Performance Data Transmission Inter-Symbol-Interference(ISI) Intellectual Property(IP) Transmitter And Receiver Simulation Results Biometric Features Capacitive Coupling Detection Probability Energy Loss Iot Devices Test Structures Measurement Results MPEG-2 Rate Performance Capacitor Voltage Implantable Devices Mpeg-4 Instruction Sets Wireless Technology Hardware Accelerator Bio-Signal Acquisition Clock Frequency Digital Communication Increasing Temperature Video Compression Transmission Channel Load Current Maximum Data Rate Root-Mean-Square Delay Spread Ultra-Low-Energy High Data Rate Electronic Design Automation(EDA) Training And Testing Performance Evaluation Performance Analysis Support Vectormachine(SVM) Simd Architecture Energy Harvester Energy Harvesting(EH) Measurement And Analysis Open Circuit Voltage(VOC) User Recognition Active Devices Active Period Event-Driven Measurement Setup Specific Applications Unique Characteristics Wavelet Features Arm Processor Highly Reliable Ap Soc Baseline Profile Biological Characteristics Biometric System Cross-Layer Optimization Capacitor Bank Conventional Test Compressed Images Context Adaptive Chip Multicore Processor(CMP) Energy Input Frame Detection Frequency Selective Digital Transmission Fast Settling Time Feasibility Study Transceiver Design Test Circuit Load Conditions K-Nearest Neighbors (Knn) Algorithm Massively Parallel Memory Contention Optimum Load Noc Simulator Prototype Development Practical Design Radio Frequency(RF) System Design Specific Design Semiconductor Technology Software Profiling Second Transition Spike-Frequency Adaptation Stable Control Design Methodology In-Depth Analysis United States Power Management Unit Head-Mounted High Resolution Image High Performance Hardware Structure Application Specific Processor Biological Behavior Clock And Data Recovery Communication Performance Capsule Endoscope Convolution Neural Network(CNN) Charge Pump Data Center Creative Technology Digital To Analog Converter Design Spaces Electrical Power Electrode Surface Electric Power Dynamic Control Energy Saving Fifth Generation (5g) Cellular Ip Video Integrate-And-Fire Model Mean Square Error(MSE) Memory Management Unit Multicore Baseband Nano Second Network Configuration Processor Architecture Platform Architecture Phased Antenna Array Power System-On-Chip Positive Effects Peak Efficiency Selection Algorithm Semiconductor Manufacturing Silicon Carbide(3C-SiC) Series-Connected System Development SP800-90B Wireless Connection Mobile Virtual Reality Digital Controller Commercial Products Statistical Analysis Adaptive Algorithm Approximate Computation Beta Source Biometric Recognition Channel Analysis Carrier-To-Noise Ratio(CNR) Compressed Domain Electronic Devices Energy Conversion Domain Analysis Fixed-Point Flexible Router Integrated Circuit Video Decoder Thermoelectric Effects Low Supply Voltage Modulation Method Mnist Database Mapping Method Multi-Level Memory Bottleneck Network Applications Network Architecture Peak Detection Resource Utilisation Stored Energy Signal-To-Noise State-Of-The-Art Search Method Vliw Processor Wireless Link Voltage Drop Wide Load Range Hodgkin-Huxley Neuron Model Handwritten Digit Hardware Complexity Hardware And Software Approximate Computing Analog Amplifier Accelerator Design Average Energy Consumption Comprehensive Study Control Signal Generation Chip Architecture Down-Chirp Design Exploration Experimental Setup Efficiency Of System Entropy Estimation Frequency Calibration Feature Vector Fast Motion Gradient Descent Inline Assembly Low Duty Load Circuit Leaky Integrate-And-Fire Modular Structure Measurement And Evaluation Multiple Interfaces Memory Footprint Multi-Core Architecture Motion Detection Multiple Channels Operating Characteristics Processor Design Path Gain Parallel Connection Quad-Core Signal Detection Signal Distortion Signal Attenuation Representative Feature Short-Circuit Current Sensor Applications Single-Precision Starting Point Security System Various Approaches Virtual Prototype Voltage Range True Random Number Generation Model-Based High Energy Efficiency High Efficiency Human Recognition Artificial Neural Networks Augmented Reality(AR) Attenuation Effect Analog Front-End Automatic Control Classification Accuracy Charging Efficiency Capacitor Array Continuous Phase Capsule Endoscopy Complementary Metal-Oxide-Semiconductor(CMOS) Conventional Methods Communication Overhead Dc-Dc Converters Dispersive Effect Dc Voltage Energy Recycling External Control Frequency Scaling Frequency Range Image Data Image Processing Inter-Core Communication Impulse Response Measurement Iterative Algorithms Low-Power Operation Mobile Services Mmu-Less Embedded Systems Ni Foil Output Voltage Ripple Operating Frequency Power Reduction Processing Information Parallel Decoding Performance Degradation Parallel Connected Performance Loss Power Efficiency Queue Stability Receiver Operating Characteristic(ROC) Reconfigurable Structure Signal Modulation Single Core Signal Noise Ratio(SNR) Systems-On-Chip Shared Memory Virtualized System Voltage Boosting 130 Nm Communication Reliability Spike-Timing-Dependent Plasticity Application-Specific Instruction-Set Processor Adaptive Filter Body Biasing Cache Coherence Chirp Signals Circuit Simulation Compression Ratio Computationally Expensive Detection Method Dynamic Voltage Design Environment Electrode Size Environmental Variations Effectiveness Evaluation Example-Based Floating Point Fpga Prototype Filter Approach Lock Time Labview Environment Maximum Efficiency Minimizing Power Multiple Media Neural Network Training Operating Efficiency Operating Characteristic Curves Power Allocation(PA) Power Range Receive Filter Receiving Channel Software Optimization Virtual Platform Virtual Model Time Based 5g Cellular Networks 60 Ghz Instruction Set Architecture Carry Out Video Codec Unsupervised Training High Reliability Charging Method Communication System Case Studies Design Guidelines Digital Signal Processing Delay Profiles Decision Boundary Development Process Energy Management Circuit Energy Converter End Module Frequency Shift Frequency Response(FreRes) Formula Presented Functional Verification Full-Custom Ieee Standards Input Voltage Image Compression Transfer Function(DTF) Threshold Range Low Power Processors Low-Power System Maximum Likelihood (Ml) Detector Measured Data Multi-Source Machine Learning Algorithms Minimum Entropy Mobile System Neural System Non-Uniform Off-Chip Network Processing Neuromorphic Systems On-Chip Infrastructure Object Region Phase Inversion Process Level Power Delay Profile(PDP) Process Information Receiver Front-End Signal Processing Module System-Level Virtualization Speed-Up Xilinx Virtex Video Surveillance System Time Average Temperature Characteristics Transition Time Total Power 5g Millimeter-Wave State University 48 V Pilot Study High-Speed Wireless Huge Data Accelerator Architecture Bulk Cmos Conventional Energy Computer Architecture Configurable Processor Custom Instructions Development Cost Duty Ratio Design Parameters Driving Characteristics Design Requirements End Nodes Experiment Results Energy-Aware Function Module Fully Integrated Interference Effects Transmission Section Level Control Level Of Training Maximum Power Multi-Domain Optimized Algorithm Optimization Methods Performance Emulation Router Frequency 100 Mhz System Reliability Supply Power Small-Sized Signal Processing Techniques System-Level Design Synchronization Algorithm Wearable Electronic Device Variable Precision Wireless Transmission Variable Length Code Device Location Biometric Signals Post-Fabrication