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Multicore Flow Processor with Wire-Speed Flow Admission Control
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- Authors
- Kyeong-Hwan Doo, Bin-Yeong Yoon, Bhum-Cheol Lee, Soon-Seok Lee, Man Soo Han, Whan-Woo Kim
- Issue Date
- 2012-11
- Citation
- ETRI Journal, v.34, no.6, pp.827-837
- ISSN
- 1225-6463
- Publisher
- 한국전자통신연구원 (ETRI)
- Language
- English
- Type
- Journal Article
- Abstract
- We propose a flow admission control (FAC) for setting up a wire-speed connection for new flows based on their negotiated bandwidth. It also terminates a flow that does not have a packet transmitted within a certain period determined by the users. The FAC can be used to provide a reliable transmission of user datagram and transmission control protocol applications. If the period of flows can be set to a short time period, we can monitor active flows that carry a packet over networks during the flow period. Such powerful flow management can also be applied to security systems to detect a denial-of-service attack. We implement a network processor called a flow management network processor (FMNP), which is the second generation of the device that supports FAC. It has forty reduced instruction set computer core processors optimized for packet processing. It is fabricated in 65-nm CMOS technology and has a 40-Gbps process performance. We prove that a flow router equipped with an FMNP is better than legacy systems in terms of throughput and packet loss. © 2012 ETRI.
- KSP Keywords
- Admission control(AC), CMOS Technology, Denial of service attack, Flow Admission Control, Flow Router, Legacy Systems, Reduced Instruction set computer(RISC), Second generation(2G), Setting up, Short time, Throughput and packet loss