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Journal Article A Novel Process for Fabricating a High Density Trench MOSFETs for DC-DC Converters
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Authors
Jong Dae Kim, Tae Moon Roh, Sang-Gi Kim, Il-Yong Park, Yil Suk Yang, Dae-Woo Lee, Jin-Gun Koo, Kyoung-Ik Cho, Young Il Kang
Issue Date
2002-10
Citation
ETRI Journal, v.24, no.5, pp.333-340
ISSN
1225-6463
Publisher
한국전자통신연구원 (ETRI)
Language
English
Type
Journal Article
DOI
https://dx.doi.org/10.4218/etrij.02.0102.0501
Abstract
We propose a new process technique for fabricating very high-density trench MOSFETs using 3 mask layers with oxide spacers and a self-aligned technique. This technique reduces the device size in trench width, source, and p-body region with a resulting increase in cell density and current driving capability as well as cost-effective production capability. We were able to obtain a higher breakdown voltage with uniform oxide grown along the trench surface. The channel density of the trench DMOSFET with a cell pitch of 2.3-2.4 μm was 100 Mcell/in2 and a specific on-resistance of 0.41 m廓cm2 was obtained under a blocking voltage of 43 V.
KSP Keywords
3 V, Blocking voltage, Breakdown voltage(BDV), Cell density, Channel Density, DC-DC Converters, Device size, Effective production, High-density, Novel process, Process technique