상세정보
학술지
Pipelined Scheduling of Functional HW/SW Modules for Platform-Based SoC Design
- 발행일
- 200510
- 출처
- ETRI Journal, v.27 no.5, pp.533-538
- ISSN
- 1225-6463
- 출판사
- 한국전자통신연구원 (ETRI)
- 협약과제
- 04MB5400, 저전력 그래픽처리 SoC Platform, 정희범
- 초록
- We developed a pipelined scheduling technique of functional hardware and software modules for platform-based system-on-a-chip (SoC) designs. It is based on a modified list scheduling algorithm. We used the pipelined scheduling technique for a performance analysis of an MPEG4 video encoder application. Then, we applied it for architecture exploration to achieve a better performance. In our experiments, the modified SoC platform with 6 pipelines for the 32-bit dual layer architecture shows a 118% improvement in performance compared to the given basic SoC platform with 4 pipelines for the 16-bit single-layer architecture.
- KSP 제안 키워드
- Dual layer, Functional Hardware, Layer architecture, List scheduling algorithm, Performance analysis, Pipelined scheduling, Platform-based, Scheduling technique, Single-layer, SoC Design, System-on-a-Chip