08MR4500, Development of Spectrum Engineering and Millimeterwave Utiliziing Technology,
Kim Chang-Joo
Abstract
본 논문에서는 60 GHz 대역에서 동작하는 WPAN용 수신기에 필요한 저잡음 증폭기와 하향 주파수 혼합기를 90 nm CMOS 공정을 이용하여 설계하고 제작한 결과를 보인다. 우선 각 소자에 사용될 트랜지스터의 특성을 추출하기 위해 원하는 바이어스 조건에서 cascode 구조의 S-parameter를 측정했으며, 이 때 사용된 RF 패드를 따로 측정하여 그 영향을 제거함으로써 트랜지스터만의 특성을 찾아내었다. 저잡음 증폭기는 3단의 cascode 구조를 사용했으며, 측정 결과 25 dB 이득과 7 dB 이하의 잡음지수 결과를 얻었다. 그리고 하향 주파수 혼합기는 LO의 입력에 balun을 사용한 balanced 구조로 측정 결과 IF 주파수(8.5~11.5 GHz) 범위내에서 12.5 dB의 변환 손실과 ?7 dBm의 입력 P1dB을 나타내었다. 제작된 저잡음 증폭기 및 하향 주파수 혼합기의 크기와 소모 전력은 각각 0.8×0.6 ㎟에 43 mW와 0.85×0.85 ㎟에 1.2 mW이다.
KSP Keywords
5 GHz, 60 GHz, 90 nm CMOS
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