상세정보
학술지
The Characteristics of Seebeck Coefficient in Silicon Nanowires Manufactured by CMOS Compatible Process
- 발행일
- 201007
- 출처
- Nanoscale Research Letters, v.5 no.10, pp.1654-1657
- ISSN
- 1931-7573
- 출판사
- Springer
- 협약과제
- 10ZE1100, ETRI 연구역량 강화를 위한 R&D체계 구축 및 Seed형 기술개발을 위한 창의형 연구 사업, 현창희
- 초록
- Silicon nanowires are patterned down to 30 nm using complementary metal-oxide-semiconductor (CMOS) compatible process. The electrical conductivities of n-/p-leg nanowires are extracted with the variation of width. Using this structure, Seebeck coefficients are measured. The obtained maximum Seebeck coefficient values are 122 μV/K for p-leg and -94 μV/K for n-leg. The maximum attainable power factor is 0.74 mW/m K 2 at room temperature. © 2010 The Author(s).
- KSP 제안 키워드
- CMOS compatible process, Complementary metal-oxide-semiconductor(CMOS), Electrical conductivity(EC), Metal-oxide(MOX), Power factor(P.F), Room-temperature, Seebeck coefficient, Silicon nanowires(SiNWs)