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Detail
Journal Article
The Characteristics of Seebeck Coefficient in Silicon Nanowires Manufactured by CMOS Compatible Process
- Issue Date
- 2010-07
- Citation
- Nanoscale Research Letters, v.5, no.10, pp.1654-1657
- ISSN
- 1931-7573
- Publisher
- Springer
- Language
- English
- Type
- Journal Article
- Abstract
- Silicon nanowires are patterned down to 30 nm using complementary metal-oxide-semiconductor (CMOS) compatible process. The electrical conductivities of n-/p-leg nanowires are extracted with the variation of width. Using this structure, Seebeck coefficients are measured. The obtained maximum Seebeck coefficient values are 122 μV/K for p-leg and -94 μV/K for n-leg. The maximum attainable power factor is 0.74 mW/m K 2 at room temperature. © 2010 The Author(s).
- KSP Keywords
- CMOS compatible process, Complementary metal-oxide-semiconductor(CMOS), Electrical Conductivity, Metal-oxide(MOX), Power factor(P.F), Room temperature, Seebeck coefficient, Silicon nanowires(SiNWs)
This work is distributed under the term of Creative Commons License (CCL)
(CC BY)
(CC BY)
