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학술지 5.2 mW 61 dB SNDR 15 MHz Bandwidth CT ΔΣ Modulator Using Single Operational Amplifier and Single Feedback DAC
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저자
조영균, 박봉혁, 김철영
발행일
201604
출처
ETRI Journal, v.38 no.2, pp.217-226
ISSN
1225-6463
출판사
한국전자통신연구원 (ETRI)
DOI
https://dx.doi.org/10.4218/etrij.16.2515.0010
협약과제
15MI1500, 차세대 무선통신용 반도체 기반 스마트 안테나 기술 개발, 박봉혁
초록
We propose an architecture that reduces the power consumption and active area of such a modulator through a reduction in the number of active components and a simplification of the topology. The proposed architecture reduces the power consumption and active area by reducing the number of active components and simplifying the modulator topology. A novel second-order loop filter that uses a single operational amplifier resonator reduces the number of active elements and enhances the controllability of the transfer function. A trapezoidal-shape half-delayed return-to-zero feedback DAC eliminates the loop-delay compensation circuitry and improves pulse-delay sensitivity. These simple features of the modulator allow higher frequency operation and more design flexibility. Implemented in a 130 nm CMOS technology, the prototype modulator occupies an active area of 0.098 mm2 and consumes 5.23 mW power from a 1.2 V supply. It achieves a dynamic range of 62 dB and a peak SNDR of 60.95 dB over a 15 MHz signal bandwidth with a sampling frequency of 780 MHz. The figure-ofmerit of the modulator is 191 fJ/conversion-step.
키워드
Second-order loop filter, Single operational amplifier resonator, 灌?? modulator
KSP 제안 키워드
130 nm, Active Element, Active area, Active components, CMOS Technology, Compensation circuitry, Design flexibility, MHz bandwidth, Operational Amplifiers(Op-Amps), Power Consumption, Sampling frequency