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Journal Article 차세대 지능형 소자 구현을 위한 모노리식 3D 집적화 기술 이슈
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Authors
문제현, 남수지, 주철웅, 성치훈, 김희옥, 조성행, 박찬우
Issue Date
2021-06
Citation
전자통신동향분석, v.36, no.3, pp.12-22
ISSN
1225-6455
Publisher
한국전자통신연구원
Language
Korean
Type
Journal Article
DOI
https://dx.doi.org/10.22648/ETRI.2021.J.360302
Abstract
Since the technical realization of self-aligned planar complementary metal-oxide-semiconductor field-effect transistors in 1960s, semiconductor manufacturing has aggressively pursued scaling that fruitfully resulted in tremendous advancement in device performances and realization of features sizes smaller than 10 nm. Due to many intrinsic material and technical obstacles, continuing the scaling progress of semiconductor devices has become increasingly arduous. As an effort to circumvent the areal limit, stacking devices in a three-dimensional fashion has been suggested. This approach is commonly called monolithic three-dimensional (M3D) integration. In this work, we examined technical issues that need to be addressed and overcome to fully realize energy efficiency, short latency and cost competency. Full-fledged M3D technologies are expected to contribute to various new fields of artificial intelligence, autonomous gadgets and unknowns, which are to be discovered.
KSP Keywords
Complementary metal-oxide-semiconductor(CMOS), Energy Efficiency, Field-effect transistors(FETs), Metal-oxide(MOX), Metal-oxide-semiconductor field-effect transistor(MOSFET), Semiconductor manufacturing, Three dimensional(3D), artificial intelligence, self-Aligned, semiconductor device, technical issues
This work is distributed under the term of Korea Open Government License (KOGL)
(Type 4: : Type 1 + Commercial Use Prohibition+Change Prohibition)
Type 4: