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학술지 Switching and Heat-Dissipation Performance Analysis of an LTCC-Based Leadless Surface Mount Package
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정동윤, 장현규, 원종일, 조두형, 권성규, 이성현, 박건식, 임종원, 이용하
Journal of Semiconductor Technology and Science, v.22 no.1, pp.1-9
대한전자공학회 (IEIE)
20VU1100, 국방 무기체계용 핵심 반도체 부품 자립화 플랫폼 개발, 임종원
?볾 leadless surface mount package was developed to enhance the switching and heat-dissipation properties of a power semiconductor. The package was implemented through a low-temperature co-fired ceramic (LTCC)-based multilayer circuit substrate that could form embedded cavities. A silicon carbide (SiC) Schottky barrier diode (SBD) bare die was attached to the cavity in the LTCC substrate. Chip interconnection was realized using a wide and thick copper (Cu) clip with a low parasitic inductance and electrical resistance compared to those of a conventional wire. Silver-filled multiple vias and wide metal planes were used to reduce the electrical parasitic effects and enhance the heat-dissipation of the package. The DC and dynamic characteristics of the 600 V/10 A-class SiC SBD package involving the proposed technologies were evaluated. The dynamic test results indicated that the reverse recovery charge (Qrr) was 18.7% lower than that of a traditional TO-220 packaged product with the same bare die. Furthermore, two leadless commercial products and the proposed package prototype were applied to a power factor correction (PFC) converter, and the power loss and heat-dissipation performances were compared. The proposed package exhibited a lower loss and higher heat dissipation than those of the commercial products.
KSP 제안 키워드
Commercial products, Dynamic test, Electrical Resistance, Heat Dissipation, LTCC substrate, Low Temperature Cofired Ceramic(LTCC), Low parasitic inductance, Low temperature(LT), Parasitic effects, Performance analysis, Power factor(P.F)
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저작자 표시 - 비영리 (CC BY NC)