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Journal Article
A 120 GHz Hybrid Low Noise Amplifier in 40 nm CMOS
- Authors
- Dong Ouk Cho, In Cheol Yoo, Dong-Woo Kang, Bon Tae Koo, Chul Woo Byeon
- Issue Date
- 2024-11
- Citation
- IEEE Access, v.12, pp.168010-168017
- ISSN
- 2169-3536
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Language
- English
- Type
- Journal Article
- Abstract
- In this paper, we present a 6-stage 120 GHz hybrid low noise amplifier (LNA) for sub-THz radar systems. To enhance the noise figure (NF) and gain performance of the LNA, we propose a hybrid architecture that utilizes a combination of 2-stage single-ended and 4-stage differential common-source amplifiers. The first 2-stage single-ended common-source amplifier provides low-loss and low-noise characteristics, while the 4-stage differential common-source amplifier provides high gain, resulting in low noise and high gain performance. Implemented in a 40 nm CMOS process, the LNA occupies a chip area of 0.099 mm2 excluding the pads. The measurement results show that the proposed LNA achieves a low NF of 5.5 dB, a high gain of 27.5 dB, and an input 1-dB compression point of -29.5 dBm at 122.5 GHz with a power consumption of 27.4 mW.
This work is distributed under the term of Creative Commons License (CCL)
(CC BY NC ND)
(CC BY NC ND)
