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학술지 3-Level Envelope Delta-Sigma Modulation RF Signal Generator for High-Efficiency Transmitters
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저자
서영호, 조영균, 최성곤, 김창완
발행일
201412
출처
ETRI Journal, v.36 no.6, pp.924-930
ISSN
1225-6463
출판사
한국전자통신연구원 (ETRI)
DOI
https://dx.doi.org/10.4218/etrij.14.0114.0176
협약과제
14MI9100, (통합)초연결 스마트 모바일 서비스를 위한 5G 이동통신 핵심기술개발, 정현규
초록
This paper presents a 0.13 μm CMOS 3-level envelope delta-sigma modulation (EDSM) RF signal generator, which synthesizes a 2.6 GHz-centered fully symmetrical 3-level EDSM signal for high-efficiency power amplifier architectures. It consists of an I-Q phase modulator, a Class B wideband buffer, an up-conversion mixer, a D2S, and a Class AB wideband drive amplifier. To preserve fast phase transition in the 3-state envelope level, the wideband buffer has an RLC load and the driver amplifier uses a second-order BPF as its load to provide enough bandwidth. To achieve an accurate 3-state envelope level in the up-mixer output, the LO bias level is optimized. The I-Q phase modulator adopts a modified quadrature passive mixer topology and mitigates the I-Q crosstalk problem using a 50% duty cycle in LO clocks. The fabricated chip provides an average output power of -1.5 dBm and an error vector magnitude (EVM) of 3.89% for 3GPP LTE 64 QAM input signals with a channel bandwidth of 10/20 MHz, as well as consuming 60 mW for both channels from a 1.2 V/2.5 V supply voltage.
키워드
3GPP LTE, CMOS, EDSM, Envelope delta-sigma modulation, Polar modulator, Power amplifier, RF transmitter
KSP 제안 키워드
2.6 GHz, 3-Level, 3GPP LTE, Channel bandwidth, Class AB(CAB), Class B, Driver Amplifier, Duty cycle(DC), Output power, Passive mixer, Phase transition