Subjects : Digital logic
| Type | Year | Title | Cited | Download |
|---|---|---|---|---|
| Conference | 2001 | Design and Simulation of 622 Mb/s Burst Mode Clock Recovery Circuit Using Digital Logic Devices Jae-Seung Hwang 한국통신학회 종합 학술 발표회 (하계) 2001, pp.1743-1746 |
| Status | Year | Patent Name | Country | Family Pat. | KIPRIS |
|---|---|---|---|---|---|
| Registered | 2014 | 디지털 연산 회로의 기능 복구 장치 및 방법 | KOREA | KIPRIS |
| Type | Year | Research Project | Primary Investigator | Download |
|---|---|---|---|---|
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