Subjects : Area Reduction
| Type | Year | Title | Cited | Download |
|---|---|---|---|---|
| Conference | 2024 | An Efficient Ku-Band Two-Way Vertical-like Power-Combining Power Amplifier using Merged Inter-stage Transformers Achieving 23-23.4 dBm Psat and 45.2-46.6% Peak PAE in 65nm CMOS 김준형 Radio Frequency Integrated Circuits (RFIC) Symposium 2024, pp.299-302 | 6 | 원문 |
| Journal | 2019 | 경량 동적 엘리먼트 메칭(Dynamic Element Matching) 기술을 이용한 저전력 디지털-아날로그 변환기(DAC) 설계 윤동현 IEEE Access, v.7, pp.112617-112628 | 10 | 원문 |
| Conference | 2006 | A 5-mW 0.26-mm2 10-bit 20-MS/s Pipelined CMOS ADC with Multi-Stage Amplifier Sharing Technique Young-Deuk Jeon European Solid-State Circuits Conference (ESSCIRC) 2006, pp.544-547 | 9 | 원문 |
| Status | Year | Patent Name | Country | Family Pat. | KIPRIS |
|---|---|---|---|---|---|
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| Type | Year | Research Project | Primary Investigator | Download |
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