|
Journal
|
2012 |
A Time-to-Digital Converter Based on a Multiphase Reference Clock and a Binary Counter With a Novel Sampling Error Corrector
최광천 IEEE Transactions on Circuits and Systems II : Express Briefs, v.59, no.3, pp.143-147 |
32 |
원문
|
|
Conference
|
2009 |
Two-Parallel Concatenated BCH Super-FEC Architecture for 100-GB/S Optical Communications
윤상호 Workshop on Signal Processing Systems (SIPS) 2009, pp.36-39 |
4 |
원문
|
|
Journal
|
2007 |
A 10-bit 205-MS/s 1.0- mm2 90-nm CMOS Pipeline ADC for Flat Panel Display Applications
Seung-Chul Lee IEEE Journal of Solid-State Circuits, v.42, no.12, pp.2688-2695 |
52 |
원문
|